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Message-ID: <20250324-successful-aquatic-pudu-5a3cdb@krzk-bin>
Date: Mon, 24 Mar 2025 09:06:40 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Sai Krishna Musham <sai.krishna.musham@....com>
Cc: bhelgaas@...gle.com, lpieralisi@...nel.org, kw@...ux.com,
manivannan.sadhasivam@...aro.org, robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
cassel@...nel.org, linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, michal.simek@....com, bharat.kumar.gogada@....com,
thippeswamy.havalige@....com
Subject: Re: [PATCH v5 1/2] dt-bindings: PCI: xilinx-cpm: Add reset-gpios for
PCIe RP PERST#
On Fri, Mar 21, 2025 at 05:12:10PM +0530, Sai Krishna Musham wrote:
> Introduce `reset-gpios` property to enable GPIO-based control of
> the PCIe RP PERST# signal, generating assert and deassert signals.
>
> Traditionally, the reset was managed in hardware and enabled during
> initialization. With this patch set, the reset will be handled by the
> driver. Consequently, the `reset-gpios` property must be explicitly
> provided to ensure proper functionality.
>
> Add CPM clock and reset control registers base (`cpm_crx`) to handle
> PCIe IP reset along with PCIe RP PERST# to avoid Link Training errors.
>
> Add `cpm_crx` property between `cfg` and `cpm_csr` as required. Absence
> of this property results in an ABI break.
>
> Signed-off-by: Sai Krishna Musham <sai.krishna.musham@....com>
> ---
> Changes for v5:
> - Remove `reset-gpios` property from required as it is already present
> in pci-bus-common.yaml
> - Update commit message
> Changes for v4:
> - Add CPM clock and reset control registers base to handle PCIe IP
> reset.
> - Update commit message.
>
> Changes for v3:
> - None
>
> Changes for v2:
> - Add define from include/dt-bindings/gpio/gpio.h for PERST# polarity
> - Update commit message
> ---
> .../bindings/pci/xilinx-versal-cpm.yaml | 17 ++++++++++++-----
> 1 file changed, 12 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> index d674a24c8ccc..293df91d4e74 100644
> --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> @@ -24,15 +24,17 @@ properties:
> items:
> - description: CPM system level control and status registers.
> - description: Configuration space region and bridge registers.
> + - description: CPM clock and reset control registers.
Nothing improved.
Best regards,
Krzysztof
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