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Message-ID: <ea5de004-a26c-43a1-9408-0089fa18b44d@tuxon.dev>
Date: Mon, 24 Mar 2025 10:18:12 +0200
From: Claudiu Beznea <claudiu.beznea@...on.dev>
To: Théo Lebrun <theo.lebrun@...tlin.com>,
Andrew Lunn <andrew+netdev@...n.ch>, "David S. Miller"
<davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Nicolas Ferre <nicolas.ferre@...rochip.com>,
Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt
<palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
Alexandre Ghiti <alex@...ti.fr>, Samuel Holland <samuel.holland@...ive.com>,
Richard Cochran <richardcochran@...il.com>,
Russell King <linux@...linux.org.uk>,
Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
Vladimir Kondratiev <vladimir.kondratiev@...ileye.com>,
Gregory CLEMENT <gregory.clement@...tlin.com>
Cc: netdev@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
linux-mips@...r.kernel.org, Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
Tawfik Bayouk <tawfik.bayouk@...ileye.com>
Subject: Re: [PATCH net-next 10/13] net: macb: Add "mobileye,eyeq5-gem"
compatible
Hi, Theo,
On 21.03.2025 21:09, Théo Lebrun wrote:
> Add support for the two GEM instances inside Mobileye EyeQ5 SoCs, using
> compatible "mobileye,eyeq5-gem". With it, add a custom init sequence
> that accesses two system-controller registers.
>
> Noteworthy: NET_IP_ALIGN=2 on MIPS but the hardware does not align and
> low bits aren't configurable, so we cannot respect the requested IP
> header alignment.
>
> Signed-off-by: Théo Lebrun <theo.lebrun@...tlin.com>
> ---
> drivers/net/ethernet/cadence/macb_main.c | 95 ++++++++++++++++++++++++++++++++
> 1 file changed, 95 insertions(+)
>
> diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
> index 79161d559166478f85a6f8294d488ed961d9be7f..9f2a5bf9a5ebca5941229bd96091a0fb96f0607d 100644
> --- a/drivers/net/ethernet/cadence/macb_main.c
> +++ b/drivers/net/ethernet/cadence/macb_main.c
> @@ -22,6 +22,7 @@
> #include <linux/iopoll.h>
> #include <linux/ip.h>
> #include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> #include <linux/module.h>
> #include <linux/moduleparam.h>
> #include <linux/netdevice.h>
> @@ -34,6 +35,7 @@
> #include <linux/platform_device.h>
> #include <linux/pm_runtime.h>
> #include <linux/ptp_classify.h>
> +#include <linux/regmap.h>
> #include <linux/reset.h>
> #include <linux/slab.h>
> #include <linux/tcp.h>
> @@ -4967,6 +4969,86 @@ static int init_reset_optional(struct platform_device *pdev)
> return ret;
> }
>
> +#define EYEQ5_OLB_GP_TX_SWRST_DIS BIT(0) // Tx SW reset
> +#define EYEQ5_OLB_GP_TX_M_CLKE BIT(1) // Tx M clock enable
> +#define EYEQ5_OLB_GP_SYS_SWRST_DIS BIT(2) // Sys SW reset
> +#define EYEQ5_OLB_GP_SYS_M_CLKE BIT(3) // Sys clock enable
> +#define EYEQ5_OLB_GP_SGMII_MODE BIT(4) // SGMII mode
> +#define EYEQ5_OLB_GP_RGMII_DRV GENMASK(8, 5) // RGMII mode
> +#define EYEQ5_OLB_GP_SMA_DRV GENMASK(12, 9)
Defines starting here:
> +#define EYEQ5_OLB_GP_RGMII_PD BIT(13) // RGMII pull-down
> +#define EYEQ5_OLB_GP_MDIO_PU BIT(14) // RGMII pull-up
> +#define EYEQ5_OLB_GP_RGMII_RX_ST BIT(15) // Schmitt trigger on RGMII Rx
> +#define EYEQ5_OLB_GP_RGMII_TX_ST BIT(16) // Schmitt trigger on RGMII Tx
> +#define EYEQ5_OLB_GP_MDIO_ST BIT(17)
> +#define EYEQ5_OLB_GP_MDC_ST BIT(18)
> +#define EYEQ5_OLB_GP_MBIST_ENABLE BIT(19)
ending here are unused.
> +
> +#define EYEQ5_OLB_SGMII_PWR_EN BIT(0)
> +#define EYEQ5_OLB_SGMII_RST_DIS BIT(1)
> +#define EYEQ5_OLB_SGMII_PLL_EN BIT(2)
> +#define EYEQ5_OLB_SGMII_SIG_DET_SW BIT(3)
> +#define EYEQ5_OLB_SGMII_PWR_STATE_MASK GENMASK(8, 4)
Unused
> +#define EYEQ5_OLB_SGMII_PWR_STATE BIT(4)
> +#define EYEQ5_OLB_SGMII_TX_ELECT_IDLE BIT(9) // Tx elect idle
Unused
> +#define EYEQ5_OLB_SGMII_POWER_ACK BIT(16)
Unused
> +#define EYEQ5_OLB_SGMII_PLL_ACK BIT(18)
> +#define EYEQ5_OLB_SGMII_SIG_DET BIT(19)
> +#define EYEQ5_OLB_SGMII_PWR_STATE_ACK GENMASK(24, 20)
Unused.
> +
> +static int eyeq5_init(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct net_device *netdev = platform_get_drvdata(pdev);
> + struct macb *bp = netdev_priv(netdev);
> + struct device_node *np = dev->of_node;
> + unsigned int gp, sgmii;
> + struct regmap *regmap;
> + unsigned int args[2];
> + unsigned int reg;
> + int ret;
> +
> + regmap = syscon_regmap_lookup_by_phandle_args(np, "mobileye,olb", 2, args);
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
> +
> + gp = args[0];
> + sgmii = args[1];
> +
> + /* Forced reset */
> + regmap_write(regmap, gp, 0);
> + regmap_write(regmap, sgmii, 0);
> + usleep_range(5, 20);
> +
> + if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
> + regmap_write(regmap, gp, EYEQ5_OLB_GP_SGMII_MODE);
> +
> + reg = EYEQ5_OLB_SGMII_PWR_EN | EYEQ5_OLB_SGMII_RST_DIS |
> + EYEQ5_OLB_SGMII_PLL_EN;
> + regmap_write(regmap, sgmii, reg);
> +
> + ret = regmap_read_poll_timeout(regmap, sgmii, reg,
> + reg & EYEQ5_OLB_SGMII_PLL_ACK,
> + 1, 100);
> + if (ret)
> + return dev_err_probe(dev, ret, "PLL timeout");
> +
> + regmap_read(regmap, sgmii, ®);
> + reg |= EYEQ5_OLB_SGMII_PWR_STATE | EYEQ5_OLB_SGMII_SIG_DET_SW;
> + regmap_write(regmap, sgmii, reg);
You can use regmap_update_bits() here.
> + }
> +
> + regmap_read(regmap, gp, ®);
> + reg &= ~EYEQ5_OLB_GP_RGMII_DRV;
> + if (phy_interface_mode_is_rgmii(bp->phy_interface))
> + reg |= FIELD_PREP(EYEQ5_OLB_GP_RGMII_DRV, 0x9);
> + reg |= EYEQ5_OLB_GP_TX_SWRST_DIS | EYEQ5_OLB_GP_TX_M_CLKE;
> + reg |= EYEQ5_OLB_GP_SYS_SWRST_DIS | EYEQ5_OLB_GP_SYS_M_CLKE;
> + regmap_write(regmap, gp, reg);
To me it looks like this code could be abstracted as a phy driver. E.g.,
check the init_reset_optional() and its usage on "cdns,zynqmp-gem" (phy
driver here: drivers/phy/xilinx/phy-zynqmp.c).
> +
> + return macb_init(pdev);
> +}
> +
> static const struct macb_usrio_config sama7g5_usrio = {
> .mii = 0,
> .rmii = 1,
> @@ -5135,6 +5217,18 @@ static const struct macb_config versal_config = {
> .usrio = &macb_default_usrio,
> };
>
> +static const struct macb_config eyeq5_config = {
> + .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
> + MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_QUEUE_DISABLE |
> + MACB_CAPS_NO_LSO,
> + .hw_ip_align = 0,
> + .dma_burst_length = 16,
> + .clk_init = macb_clk_init,
> + .init = eyeq5_init,
> + .jumbo_max_len = 10240,
> + .usrio = &macb_default_usrio,
> +};
> +
> static const struct of_device_id macb_dt_ids[] = {
> { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
> { .compatible = "cdns,macb" },
> @@ -5152,6 +5246,7 @@ static const struct of_device_id macb_dt_ids[] = {
> { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config}, /* deprecated */
> { .compatible = "cdns,zynq-gem", .data = &zynq_config }, /* deprecated */
> { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
> + { .compatible = "mobileye,eyeq5-gem", .data = &eyeq5_config },
Maybe move it after microchip to have it a bit sorted.
Thank you,
Claudiu
> { .compatible = "microchip,mpfs-macb", .data = &mpfs_config },
> { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config },
> { .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config },
>
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