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<DU0PR04MB949673D7E71316D001C3872A90A72@DU0PR04MB9496.eurprd04.prod.outlook.com>
Date: Tue, 25 Mar 2025 08:40:10 +0000
From: Bough Chen <haibo.chen@....com>
To: Luke Wang <ziniu.wang_1@....com>, "adrian.hunter@...el.com"
<adrian.hunter@...el.com>, "ulf.hansson@...aro.org" <ulf.hansson@...aro.org>
CC: "shawnguo@...nel.org" <shawnguo@...nel.org>, "s.hauer@...gutronix.de"
<s.hauer@...gutronix.de>, "kernel@...gutronix.de" <kernel@...gutronix.de>,
"festevam@...il.com" <festevam@...il.com>, "imx@...ts.linux.dev"
<imx@...ts.linux.dev>, "linux-mmc@...r.kernel.org"
<linux-mmc@...r.kernel.org>, dl-S32 <S32@....com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>, "linux-kernel@...r.kernel.org"
<linux-kernel@...r.kernel.org>
Subject: RE: [PATCH 2/2] mmc: sdhci-esdhc-imx: calclute data timeout value
based on clock
> -----Original Message-----
> From: Luke Wang <ziniu.wang_1@....com>
> Sent: 2025年3月24日 17:24
> To: adrian.hunter@...el.com; ulf.hansson@...aro.org; Bough Chen
> <haibo.chen@....com>
> Cc: shawnguo@...nel.org; s.hauer@...gutronix.de; kernel@...gutronix.de;
> festevam@...il.com; imx@...ts.linux.dev; linux-mmc@...r.kernel.org; dl-S32
> <S32@....com>; linux-arm-kernel@...ts.infradead.org;
> linux-kernel@...r.kernel.org
> Subject: [PATCH 2/2] mmc: sdhci-esdhc-imx: calclute data timeout value based
> on clock
>
> From: Luke Wang <ziniu.wang_1@....com>
>
> Calclute data timeout value based on clock instead of using max value.
>
> Signed-off-by: Luke Wang <ziniu.wang_1@....com>
> ---
> drivers/mmc/host/sdhci-esdhc-imx.c | 15 +++++++++++----
> 1 file changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
> b/drivers/mmc/host/sdhci-esdhc-imx.c
> index ff78a7c6a04c..e7316ecff64e 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -31,6 +31,7 @@
> #include "cqhci.h"
>
> #define ESDHC_SYS_CTRL_DTOCV_MASK GENMASK(19, 16)
> +#define ESDHC_SYS_CTRL_DTOCV_SHIFT 16
> #define ESDHC_SYS_CTRL_IPP_RST_N BIT(23)
> #define ESDHC_CTRL_D3CD 0x08
> #define ESDHC_BURST_LEN_EN_INCR (1 << 27)
> @@ -1387,12 +1388,16 @@ static unsigned int
> esdhc_get_max_timeout_count(struct sdhci_host *host)
>
> static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command
> *cmd) {
> - struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> - struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
> + bool too_big = false;
> + u8 count = sdhci_calc_timeout(host, cmd, &too_big);
>
> - /* use maximum timeout counter */
> + /*
> + * ESDHC_SYSTEM_CONTROL bit[23] used to control hardware reset
> + * pin of the card. Write 0 to bit[23] will reset the card.
> + * Only write DTOCV filed here.
> + */
No need to mention the bit[23] here, this is a bit confuse here.
Just drop the comment here.
Then for this patch:
Reviewed-by: Haibo Chen <haibo.chen@....com>
Regards
Haibo Chen
> esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
> - esdhc_is_usdhc(imx_data) ? 0xF0000 : 0xE0000,
> + count << ESDHC_SYS_CTRL_DTOCV_SHIFT,
> ESDHC_SYSTEM_CONTROL);
> }
>
> @@ -1777,6 +1782,8 @@ static int sdhci_esdhc_imx_probe(struct
> platform_device *pdev)
> * to distinguish the card type.
> */
> host->mmc_host_ops.init_card = usdhc_init_card;
> +
> + host->max_timeout_count = 0xF;
> }
>
> if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
> --
> 2.34.1
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