linux-kernel - Re: [PATCH v1 0/5] Add snps,dis_u3_susphy

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Message-ID: <vy62ivsp7ibgotyczg7tzmxtirwwhx7kwhkatsltsprtsoqinb@5ctysskl76rj>
Date: Wed, 26 Mar 2025 16:35:36 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Krishna Kurapati <krishna.kurapati@....qualcomm.com>
Cc: Prashanth K <prashanth.k@....qualcomm.com>,
        Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        cros-qcom-dts-watchers@...omium.org, linux-arm-msm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1 0/5] Add snps,dis_u3_susphy_quirk for some QC targets

On Wed, Mar 26, 2025 at 10:52:46AM +0530, Krishna Kurapati wrote:
> 
> 
> On 3/26/2025 5:51 AM, Dmitry Baryshkov wrote:
> > On Tue, Mar 25, 2025 at 08:31:55PM +0530, Prashanth K wrote:
> > > 
> > > 
> > > On 25-03-25 08:11 pm, Konrad Dybcio wrote:
> > > > On 3/25/25 1:30 PM, Prashanth K wrote:
> > > > > During device mode initialization on certain QC targets, before the
> > > > > runstop bit is set, sometimes it's observed that the GEVNTADR{LO/HI}
> > > > > register write fails. As a result, GEVTADDR registers are still 0x0.
> > > > > Upon setting runstop bit, DWC3 controller attempts to write the new
> > > > > events to address 0x0, causing an SMMU fault and system crash. More
> > > > > info about the crash at [1].
> > > > > 
> > > > > This was initially observed on SM8450 and later reported on few
> > > > > other targets as well. As suggested by Qualcomm HW team, clearing
> > > > > the GUSB3PIPECTL.SUSPHY bit resolves the issue by preventing register
> > > > > write failures. Address this by setting the snps,dis_u3_susphy_quirk
> > > > > to keep the GUSB3PIPECTL.SUSPHY bit cleared. This change was tested
> > > > > on multiple targets (SM8350, SM8450 QCS615 etc.) for over an year
> > > > > and hasn't exhibited any side effects.
> > > > > 
> > > > > [1]: https://lore.kernel.org/all/fa94cbc9-e637-ba9b-8ec8-67c6955eca98@quicinc.com/
> > > > > 
> > > > > Prashanth K (3):
> > > > >    arm64: dts: qcom: sm8150: Add snps,dis_u3_susphy_quirk
> > > > >    arm64: dts: qcom: sm8350: Add snps,dis_u3_susphy_quirk
> > > > >    arm64: dts: qcom: sm8450: Add snps,dis_u3_susphy_quirk
> > 
> > It is hard to belive that this quirk is to be set for SM8150, SM8350,
> > SM8450, but not SM8250.
> > 
> 
> At the moment we wanted to add this quirk for targets where issue has shown
> up either internal to QC or at customer's end. But the issue didn't come up
> on SM8250/ SM8550/ SM8650 so far either from customer end or ours. Would
> like to update for other targets on need basis.

I'm not questioning SM8[56]50, but not seeing SM8250 here is really
doubtful.

-- 
With best wishes
Dmitry