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Message-ID: <174524552575.708487.5624208070172830014.b4-ty@kernel.org>
Date: Mon, 21 Apr 2025 09:25:31 -0500
From: Bjorn Andersson <andersson@...nel.org>
To: Konrad Dybcio <konradybcio@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Prashanth K <prashanth.k@....qualcomm.com>
Cc: cros-qcom-dts-watchers@...omium.org,
linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1 0/5] Add snps,dis_u3_susphy_quirk for some QC targets
On Tue, 25 Mar 2025 18:00:14 +0530, Prashanth K wrote:
> During device mode initialization on certain QC targets, before the
> runstop bit is set, sometimes it's observed that the GEVNTADR{LO/HI}
> register write fails. As a result, GEVTADDR registers are still 0x0.
> Upon setting runstop bit, DWC3 controller attempts to write the new
> events to address 0x0, causing an SMMU fault and system crash. More
> info about the crash at [1].
>
> [...]
Applied, thanks!
[1/5] arm64: dts: qcom: sm8150: Add snps,dis_u3_susphy_quirk
commit: 9bdbd5286ea597db6131c197ae9ee8614cce1890
[2/5] arm64: dts: qcom: sm8350: Add snps,dis_u3_susphy_quirk
commit: a7dac91e56ae58e1479002e5b94fab73039f2e29
[3/5] arm64: dts: qcom: sm8450: Add snps,dis_u3_susphy_quirk
commit: 9588f10adb5b67bea7eeebed2490c20dfbe82e77
[4/5] arm64: dts: qcom: qcs615: Add snps,dis_u3_susphy_quirk
commit: ad2011e02dab5ccc9f38848a3d909855a4ae7c8f
[5/5] arm64: dts: qcom: qdu1000: Add snps,dis_u3_susphy_quirk
commit: 25eee6c64376fcdc375b97c7e1f105e132654563
Best regards,
--
Bjorn Andersson <andersson@...nel.org>
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