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Message-ID:
<CH2PPF4D26F8E1C1CBD2A866C59AA55CD7AA2A12@CH2PPF4D26F8E1C.namprd07.prod.outlook.com>
Date: Thu, 27 Mar 2025 11:19:47 +0000
From: Manikandan Karunakaran Pillai <mpillai@...ence.com>
To: "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
"lpieralisi@...nel.org"
<lpieralisi@...nel.org>,
"kw@...ux.com" <kw@...ux.com>,
"manivannan.sadhasivam@...aro.org" <manivannan.sadhasivam@...aro.org>,
"robh@...nel.org" <robh@...nel.org>,
"krzk+dt@...nel.org"
<krzk+dt@...nel.org>,
"conor+dt@...nel.org" <conor+dt@...nel.org>
CC: "manivannan.sadhasivam@...aro.org" <manivannan.sadhasivam@...aro.org>,
"robh@...nel.org" <robh@...nel.org>,
"linux-pci@...r.kernel.org"
<linux-pci@...r.kernel.org>,
"devicetree@...r.kernel.org"
<devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org"
<linux-kernel@...r.kernel.org>
Subject: [PATCH 1/7] dt-bindings: pci: cadence: Extend compatible for new
platform configurations
Document the compatible property for the newly added values for PCIe EP and
RP configurations. Fix the compilation issues that came up for the existing
Cadence bindings
Signed-off-by: Manikandan K Pillai <mpillai@...ence.com>
---
.../bindings/pci/cdns,cdns-pcie-ep.yaml | 12 +-
.../bindings/pci/cdns,cdns-pcie-host.yaml | 119 +++++++++++++++---
2 files changed, 110 insertions(+), 21 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
index 98651ab22103..aa4ad69a9b71 100644
--- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
@@ -7,14 +7,22 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cadence PCIe EP Controller
maintainers:
- - Tom Joseph <tjoseph@...ence.com>
+ - Manikandan K Pillai <mpillai@...ence.com>
allOf:
- $ref: cdns-pcie-ep.yaml#
properties:
compatible:
- const: cdns,cdns-pcie-ep
+ oneOf:
+ - const: cdns,cdns-pcie-ep
+ - const: cdns,cdns-pcie-hpa-ep
+ - const: cdns,cdns-cix-pcie-hpa-ep
+ - description: PCIe EP controller from cadence
+ items:
+ - const: cdns,cdns-pcie-ep
+ - const: cdns,cdns-pcie-hpa-ep
+ - const: cdns,cdns-cix-pcie-hpa-ep
reg:
maxItems: 2
diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
index a8190d9b100f..bb7ffb9ddaf9 100644
--- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
+++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
@@ -7,16 +7,30 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cadence PCIe host controller
maintainers:
- - Tom Joseph <tjoseph@...ence.com>
+ - Manikandan K Pillai <mpillai@...ence.com>
allOf:
- - $ref: cdns-pcie-host.yaml#
+ - $ref: cdns-pcie.yaml#
properties:
+ "#size-cells":
+ const: 2
+ "#address-cells":
+ const: 3
+
compatible:
- const: cdns,cdns-pcie-host
+ oneOf:
+ - const: cdns,cdns-pcie-host
+ - const: cdns,cdns-pcie-hpa-host
+ - const: cdns,cdns-cix-pcie-hpa-host
+ - description: PCIe RP controller from cadence
+ items:
+ - const: cdns,cdns-pcie-host
+ - const: cdns,cdns-pcie-hpa-host
+ - const: cdns,cdns-cix-pcie-hpa-host
reg:
+ minItems: 1
maxItems: 2
reg-names:
@@ -24,6 +38,74 @@ properties:
- const: reg
- const: cfg
+ device_type:
+ const: pci
+
+ vendor-id:
+ const: 0x17cd
+
+ device-id:
+ enum:
+ - 0x0200
+
+ "#interrupt-cells": true
+
+ interrupt-map:
+ minItems: 1
+ maxItems: 8
+
+ interrupt-map-mask:
+ items:
+ - const: 0
+ - const: 0
+ - const: 0
+ - const: 7
+
+ interrupts:
+ minItems: 1
+ maxItems: 8
+
+ interrupt-names:
+ items:
+ - const: msi1
+ - const: msi0
+
+ linux,pci-domain:
+ description:
+ If present this property assigns a fixed PCI domain number to a PCI
+ Endpoint Controller, otherwise an unstable (across boots) unique number
+ will be assigned. It is required to either not set this property at all
+ or set it for all PCI endpoint controllers in the system, otherwise
+ potentially conflicting domain numbers may be assigned to endpoint
+ controllers. The domain number for each endpoint controller in the system
+ must be unique.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ ranges:
+ minItems: 1
+ maxItems: 8
+
+ bus-range:
+ description: |
+ The PCI bus number range; as this is a single bus, the range
+ should be specified as the same value twice.
+
+ dma-ranges:
+ description: |
+ A single range for the inbound memory region. If not supplied,
+ defaults to 1GiB at 0x40000000. Note there are hardware restrictions on
+ the allowed combinations of address and size.
+ maxItems: 1
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ items:
+ - const: pcie-phy
+
+ msi-parent: true
+
required:
- reg
- reg-names
@@ -33,37 +115,36 @@ unevaluatedProperties: false
examples:
- |
bus {
- #address-cells = <2>;
- #size-cells = <2>;
+ #address-cells = <2>;
+ #size-cells = <2>;
pcie@...00000 {
compatible = "cdns,cdns-pcie-host";
- device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
+ device_type = "pci";
bus-range = <0x0 0xff>;
linux,pci-domain = <0>;
vendor-id = <0x17cd>;
device-id = <0x0200>;
- reg = <0x0 0xfb000000 0x0 0x01000000>,
- <0x0 0x41000000 0x0 0x00001000>;
+ reg = <0xfb000000 0x01000000>,<0x41000000 0x00001000>;
reg-names = "reg", "cfg";
- ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>,
- <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>;
- dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
-
- #interrupt-cells = <0x1>;
+ ranges = <0x02000000 0x0 0x42000000 0x42000000 0x0 0x1000000 0x0>;
- interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 14 0x1>,
- <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 15 0x1>,
- <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 16 0x1>,
- <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 17 0x1>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x1 0x00000000 0x0>;
- interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ #interrupt-cells = <1>;
- msi-parent = <&its_pci>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 118 4>, <0 116 1>;
+ interrupt-names = "msi1", "msi0";
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
+ <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
+ <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
+ <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
phys = <&pcie_phy0>;
phy-names = "pcie-phy";
--
2.27.0
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