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Message-ID: <749c663e-5c6b-432f-b716-263361fbad8f@cixtech.com>
Date: Sun, 30 Mar 2025 22:59:01 +0800
From: Hans Zhang <hans.zhang@...tech.com>
To: Krzysztof Kozlowski <krzk@...nel.org>,
 Manikandan Karunakaran Pillai <mpillai@...ence.com>
Cc: "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
 "lpieralisi@...nel.org" <lpieralisi@...nel.org>, "kw@...ux.com"
 <kw@...ux.com>,
 "manivannan.sadhasivam@...aro.org" <manivannan.sadhasivam@...aro.org>,
 "robh@...nel.org" <robh@...nel.org>, "krzk+dt@...nel.org"
 <krzk+dt@...nel.org>, "conor+dt@...nel.org" <conor+dt@...nel.org>,
 "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
 "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
 "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/7] dt-bindings: pci: cadence: Extend compatible for new
 platform configurations



On 2025/3/28 17:17, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL
> 
> On 28/03/2025 09:48, Hans Zhang wrote:
>>
>>
>> On 2025/3/28 16:22, Krzysztof Kozlowski wrote:
>>> EXTERNAL EMAIL
>>>
>>> On Thu, Mar 27, 2025 at 11:19:47AM +0000, Manikandan Karunakaran Pillai wrote:
>>>> Document the compatible property for the newly added values for PCIe EP and
>>>> RP configurations. Fix the compilation issues that came up for the existing
>>>> Cadence bindings
>>>>
>>>> Signed-off-by: Manikandan K Pillai <mpillai@...ence.com>
>>>> ---
>>>>    .../bindings/pci/cdns,cdns-pcie-ep.yaml       |  12 +-
>>>>    .../bindings/pci/cdns,cdns-pcie-host.yaml     | 119 +++++++++++++++---
>>>>    2 files changed, 110 insertions(+), 21 deletions(-)
>>>
>>> One more thing: SoB mismatch. Maybe got corrupted by Microsoft (it is
>>> known), so you really need to fix your mailing setup or use b4 relay.
>>>
>>
>> Hi Krzysztof,
>>
>> I have obtained Manikandan's consent and we will collaborate to submit
> 
> It does not matter. You still need proper SoB / DCO chain. Please follow
> submitting patches.
> 

Hi Krzysztof,

Thank you very much for reminding me. I will pay attention to it.

Thanks
Hans


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