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Message-ID: <4b5fc903-f2c1-4e7e-8a4f-629566bff3ad@mailbox.org>
Date: Mon, 31 Mar 2025 15:45:18 +0200
From: Marek Vasut <marek.vasut@...lbox.org>
To: Krzysztof Kozlowski <krzk@...nel.org>
Cc: linux-arm-kernel@...ts.infradead.org, Krzysztof Wilczyński <kw@...ux.com>, Rafał Miłecki
 <rafal@...ecki.pl>, Aradhya Bhatia <a-bhatia1@...com>,
 Bjorn Helgaas <bhelgaas@...gle.com>, Conor Dooley <conor+dt@...nel.org>,
 Geert Uytterhoeven <geert+renesas@...der.be>,
 Heiko Stuebner <heiko@...ech.de>, Junhao Xie <bigfoot@...ssfun.cn>,
 Kever Yang <kever.yang@...k-chips.com>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Kuninori Morimoto <kuninori.morimoto.gx@...esas.com>,
 Lorenzo Pieralisi <lpieralisi@...nel.org>,
 Magnus Damm <magnus.damm@...il.com>,
 Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
 Neil Armstrong <neil.armstrong@...aro.org>, Rob Herring <robh@...nel.org>,
 Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
 linux-pci@...r.kernel.org, linux-renesas-soc@...r.kernel.org
Subject: Re: [PATCH 1/4] dt-bindings: PCI: rcar-gen4-pci-host: Document
 optional aux clock

On 3/31/25 10:19 AM, Krzysztof Kozlowski wrote:
> On Sun, Mar 30, 2025 at 09:56:09PM +0200, Marek Vasut wrote:
>> diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
>> index bb3f843c59d91..5e2624d4c62c7 100644
>> --- a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
>> +++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
>> @@ -46,12 +46,14 @@ properties:
>>         - const: app
>>   
>>     clocks:
>> -    maxItems: 2
>> +    minItems: 2
>> +    maxItems: 3
>>   
>>     clock-names:
> 
> missing minItems: 2
> 
> (xxx and xxx-names are always synced in dimensions)

Fixed, noted, thanks !

> I understand that clock is optional? Your diagram in commit msg suggests
> that clock is there always.

The clocks which supply the PCIe controller ("ref" clock) and PCIe bus 
("aux" clock) can be modeled as either, single clock (one clock for both 
controller AND bus, i.e. single "ref" clock), or two separate clocks 
(one for controller AND one for bus, i.e. "ref" clock AND "aux" clock).

That depends on whether the clock generator (the 9FGV0441 brick in the 
ASCII schematic in the commit message in this case) has one flip switch 
to enable both clock (controller and bus, i.e. "ref" clock only), or has 
separate flip switches to enable the different outputs (controller or 
bus, i.e. "ref" and "aux" clock).

So yes, the "aux" is optional from the software side, but on the 
hardware side, the "aux" bus clock are always there. They however do not 
always have separate flip switch to enable/disable them.

-- 
Best regards,
Marek Vasut

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