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Message-ID: <CA+V-a8vdwYBnmh3aBR37QesGgkS6+4xbL--APx_r0JXMa1uFBA@mail.gmail.com>
Date: Mon, 31 Mar 2025 15:00:35 +0100
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Biju Das <biju.das.jz@...renesas.com>
Cc: Geert Uytterhoeven <geert+renesas@...der.be>, Andrzej Hajda <andrzej.hajda@...el.com>,
Neil Armstrong <neil.armstrong@...aro.org>, Robert Foss <rfoss@...nel.org>,
"laurent.pinchart" <laurent.pinchart@...asonboard.com>, Jonas Karlman <jonas@...boo.se>,
Jernej Skrabec <jernej.skrabec@...il.com>, David Airlie <airlied@...il.com>,
Simona Vetter <simona@...ll.ch>, Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Kieran Bingham <kieran.bingham+renesas@...asonboard.com>, Stephen Boyd <sboyd@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-renesas-soc@...r.kernel.org" <linux-renesas-soc@...r.kernel.org>,
"linux-media@...r.kernel.org" <linux-media@...r.kernel.org>,
"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH 16/17] drm: renesas: rz-du: mipi_dsi: Add support for
LPCLK handling
Hi Biju,
Thank you for the review.
On Mon, Mar 31, 2025 at 1:44 PM Biju Das <biju.das.jz@...renesas.com> wrote:
>
> Hi Prabhakar,
>
> Thanks for the patch.
>
> > -----Original Message-----
> > From: Prabhakar <prabhakar.csengg@...il.com>
> > Sent: 30 March 2025 22:07
> > Subject: [PATCH 16/17] drm: renesas: rz-du: mipi_dsi: Add support for LPCLK handling
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > Introduce the `RZ_MIPI_DSI_HASLPCLK` feature flag in `rzg2l_mipi_dsi_hw_info` to indicate the need for
> > LPCLK configuration.
> >
> > On the RZ/V2H(P) SoC, the LPCLK clock rate influences the required DPHY register configuration,
> > whereas on the RZ/G2L SoC, this clock is not present. To accommodate this difference, add an `lpclk`
> > clock handle in `rzg2l_mipi_dsi` and update the probe function to conditionally acquire LPCLK if the
> > SoC supports it.
> >
> > Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@...esas.com>
> > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@...esas.com>
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > ---
> > drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-
> > du/rzg2l_mipi_dsi.c
> > index 2ca725a2ccaf..26ec0f5d065a 100644
> > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> > @@ -31,6 +31,7 @@
> > struct rzg2l_mipi_dsi;
> >
> > #define RZ_MIPI_DSI_16BPP BIT(0)
> > +#define RZ_MIPI_DSI_HASLPCLK BIT(1)
> >
> > struct rzg2l_mipi_dsi_hw_info {
> > int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, unsigned long long hsfreq_mhz); @@ -63,6 +64,7 @@
> > struct rzg2l_mipi_dsi {
> > struct drm_bridge *next_bridge;
> >
> > struct clk *vclk;
> > + struct clk *lpclk;
> >
> > enum mipi_dsi_pixel_format format;
> > unsigned int num_data_lanes;
> > @@ -792,6 +794,12 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
> > if (IS_ERR(dsi->vclk))
> > return PTR_ERR(dsi->vclk);
> >
> > + if (dsi->info->features & RZ_MIPI_DSI_HASLPCLK) {
> > + dsi->lpclk = devm_clk_get(dsi->dev, "lpclk");
>
> Maybe use devm_clk_get_optional and drop the check.
>
As the dtbs_check doesn't enforce this, `RZ_MIPI_DSI_HASLPCLK` flag
was added. Recently the same was done for the CRU [0] based on the
recent comment received.
[0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20250328173032.423322-10-tommaso.merciai.xr@bp.renesas.com/
Cheers,
Prabhakar
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