linux-kernel - Re: [PATCH 13/17] drm: renesas: rz-du: mipi_dsi: Add feature flag for 16BPP support

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Message-ID: <CA+V-a8sdFYEM6DE_ku5-FBPa6xcDmhAq6FDXiovR0VAixZds0A@mail.gmail.com>
Date: Mon, 31 Mar 2025 15:02:16 +0100
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
Cc: Andrzej Hajda <andrzej.hajda@...el.com>, Neil Armstrong <neil.armstrong@...aro.org>, 
	Robert Foss <rfoss@...nel.org>, Laurent Pinchart <Laurent.pinchart@...asonboard.com>, 
	Jonas Karlman <jonas@...boo.se>, Jernej Skrabec <jernej.skrabec@...il.com>, 
	David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>, 
	Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>, Maxime Ripard <mripard@...nel.org>, 
	Thomas Zimmermann <tzimmermann@...e.de>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Biju Das <biju.das.jz@...renesas.com>, Mauro Carvalho Chehab <mchehab@...nel.org>, 
	Kieran Bingham <kieran.bingham+renesas@...asonboard.com>, Stephen Boyd <sboyd@...nel.org>, 
	Philipp Zabel <p.zabel@...gutronix.de>, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, linux-renesas-soc@...r.kernel.org, 
	linux-media@...r.kernel.org, linux-clk@...r.kernel.org, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH 13/17] drm: renesas: rz-du: mipi_dsi: Add feature flag for
 16BPP support

Hi Geert,

Thank you for the review.

On Mon, Mar 31, 2025 at 1:29 PM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Sun, 30 Mar 2025 at 23:08, Prabhakar <prabhakar.csengg@...il.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > Introduce the `RZ_MIPI_DSI_16BPP` feature flag in `rzg2l_mipi_dsi_hw_info`
> > to indicate support for 16BPP pixel formats. The RZ/V2H(P) SoC supports
> > 16BPP, whereas this feature is missing on the RZ/G2L SoC.
> >
> > Update the `mipi_dsi_host_attach()` function to check this flag before
> > allowing 16BPP formats. If the SoC does not support 16BPP, return an error
> > to prevent incorrect format selection.
> >
> > This change enables finer-grained format support control for different
> > SoC variants.
> >
> > Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@...esas.com>
> > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@...esas.com>
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Thanks for your patch!
>
> > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> > @@ -30,6 +30,8 @@
> >
> >  struct rzg2l_mipi_dsi;
> >
> > +#define RZ_MIPI_DSI_16BPP      BIT(0)
> > +
> >  struct rzg2l_mipi_dsi_hw_info {
> >         int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, unsigned long long hsfreq_mhz);
> >         void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi);
> > @@ -38,6 +40,7 @@ struct rzg2l_mipi_dsi_hw_info {
> >         unsigned long max_dclk;
> >         unsigned long min_dclk;
> >         bool has_dphy_rstc;
> > +       u8 features;
>
> Please settle on a single solution for all features: either use a
> boolean flag to indicate 16bpp, or a feature bit to indicate the need
> for the DPHY reset signal.
>
Agreed, I will use the features flag for all.

Cheers,
Prabhakar