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Message-Id: <3f7f6ced-98e8-4101-aa83-3692e14222ca@app.fastmail.com>
Date: Tue, 01 Apr 2025 10:31:17 +0100
From: "Jiaxun Yang" <jiaxun.yang@...goat.com>
To: "Maciej W. Rozycki" <macro@...am.me.uk>,
 "Marco Crivellari" <marco.crivellari@...e.com>
Cc: "linux-mips@...r.kernel.org" <linux-mips@...r.kernel.org>,
 linux-kernel@...r.kernel.org,
 "Thomas Bogendoerfer" <tsbogend@...ha.franken.de>,
 "Frederic Weisbecker" <frederic@...nel.org>,
 "Anna-Maria Behnsen" <anna-maria@...utronix.de>,
 "Thomas Gleixner" <tglx@...utronix.de>,
 "Peter Zijlstra" <peterz@...radead.org>,
 "Huacai Chen" <chenhuacai@...nel.org>
Subject: Re: [PATCH v6 1/1] MIPS: Fix idle VS timer enqueue



在2025年3月31日星期周一 下午9:09,Maciej W. Rozycki写道:
[...]
>
>  FAOD I have one MIPS32r2 system wired for testing, but that might not be 
> the most interesting configuration to verify as it'll now just use EI/EHB 
> to enable interrupts ahead of WAIT.  I could try an R1 kernel instead, but 
> I'm not sure if it can be made to work owing to the differences in the FPU 
> between R1 and R2 for the MIPS32 ISA.  I used to have a MIPS64 (R1) system 
> there, but the CPU daughtercard sadly stopped working 3 years ago and I 
> wasn't able to repair it, owing to the lack of available spare parts (it's 
> most likely a dead CPU).

I can test on legacy (R1 version) 4Kc RTL simulator if you wish. Is there any
thing specific you want to test? I think I can try interrupt flood and see if
there is any deadlock.

The simulation is painfully slow, so I'd wish to minimize test vector.

Thanks


-- 
- Jiaxun

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