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Message-ID: <76d4cd09c609ad4b5de2dc859d0499a512df3790.camel@mediatek.com>
Date: Wed, 2 Apr 2025 03:36:38 +0000
From: Crystal Guo (郭晶) <Crystal.Guo@...iatek.com>
To: "robh@...nel.org" <robh@...nel.org>, "matthias.bgg@...il.com"
<matthias.bgg@...il.com>, AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>, "krzk@...nel.org"
<krzk@...nel.org>, "conor+dt@...nel.org" <conor+dt@...nel.org>
CC: "linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>, "linux-kernel@...r.kernel.org"
<linux-kernel@...r.kernel.org>, "linux-mediatek@...ts.infradead.org"
<linux-mediatek@...ts.infradead.org>, "devicetree@...r.kernel.org"
<devicetree@...r.kernel.org>, Project_Global_Chrome_Upstream_Group
<Project_Global_Chrome_Upstream_Group@...iatek.com>
Subject: Re: [v3,2/2] memory/mediatek: Add an interface to get current DDR
data rate
On Wed, 2025-03-26 at 11:27 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>
>
> Il 26/03/25 07:30, Crystal Guo ha scritto:
> > Add MediaTek DRAMC driver to provide an interface that can
> > obtain current DDR data rate.
> >
> > Signed-off-by: Crystal Guo <crystal.guo@...iatek.com>
> > ---
> > drivers/memory/Kconfig | 1 +
> > drivers/memory/Makefile | 1 +
> > drivers/memory/mediatek/Kconfig | 21 +++
> > drivers/memory/mediatek/Makefile | 2 +
> > drivers/memory/mediatek/mtk-dramc.c | 232
> > ++++++++++++++++++++++++++++
> > 5 files changed, 257 insertions(+)
> > create mode 100644 drivers/memory/mediatek/Kconfig
> > create mode 100644 drivers/memory/mediatek/Makefile
> > create mode 100644 drivers/memory/mediatek/mtk-dramc.c
> >
> > diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
> > index c82d8d8a16ea..b1698549ff81 100644
> > --- a/drivers/memory/Kconfig
> > +++ b/drivers/memory/Kconfig
> > @@ -227,5 +227,6 @@ config STM32_FMC2_EBI
> >
> > source "drivers/memory/samsung/Kconfig"
> > source "drivers/memory/tegra/Kconfig"
> > +source "drivers/memory/mediatek/Kconfig"
> >
> > endif
> > diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
> > index d2e6ca9abbe0..c0facf529803 100644
> > --- a/drivers/memory/Makefile
> > +++ b/drivers/memory/Makefile
> > @@ -27,6 +27,7 @@ obj-$(CONFIG_STM32_FMC2_EBI) += stm32-
> > fmc2-ebi.o
> >
> > obj-$(CONFIG_SAMSUNG_MC) += samsung/
> > obj-$(CONFIG_TEGRA_MC) += tegra/
> > +obj-$(CONFIG_MEDIATEK_MC) += mediatek/
> > obj-$(CONFIG_TI_EMIF_SRAM) += ti-emif-sram.o
> > obj-$(CONFIG_FPGA_DFL_EMIF) += dfl-emif.o
> >
> > diff --git a/drivers/memory/mediatek/Kconfig
> > b/drivers/memory/mediatek/Kconfig
> > new file mode 100644
> > index 000000000000..3f238e0d9647
> > --- /dev/null
> > +++ b/drivers/memory/mediatek/Kconfig
> > @@ -0,0 +1,21 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
> > +config MEDIATEK_MC
> > + bool "MediaTek Memory Controller support"
>
> default y
> depends on ARCH_MEDIATEK || COMPILE_TEST
>
> > + help
> > + This option allows to enable MediaTek memory controller
> > drivers,
> > + which may include controllers for DRAM or others.
> > + Select Y here if you need support for MediaTek memory
> > controller.
> > + If you don't need, select N.
> > +
> > +if MEDIATEK_MC
> > +
> > +config MTK_DRAMC
> > + tristate "MediaTek DRAMC driver"
> > + default y
> > + help
> > + This option selects the MediaTek DRAMC driver, which
> > provides
>
> This driver is for the DRAM Controller found in MediaTek
> SoCs
> and provides a sysfs interface for reporting the current
> DRAM
> data rate.
>
> The part saying select y or n can be avoided.
Ok, I will remove "select y or n" in the next version.
>
> > + an interface for reporting the current data rate of DRAM.
> > + Select Y here if you need support for the MediaTek DRAMC
> > driver.
> > + If you don't need, select N.
> > +
> > +endif
> > diff --git a/drivers/memory/mediatek/Makefile
> > b/drivers/memory/mediatek/Makefile
> > new file mode 100644
> > index 000000000000..a1395fc55b41
> > --- /dev/null
> > +++ b/drivers/memory/mediatek/Makefile
> > @@ -0,0 +1,2 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +obj-$(CONFIG_MTK_DRAMC) += mtk-dramc.o
> > diff --git a/drivers/memory/mediatek/mtk-dramc.c
> > b/drivers/memory/mediatek/mtk-dramc.c
> > new file mode 100644
> > index 000000000000..22042c9d8e42
> > --- /dev/null
> > +++ b/drivers/memory/mediatek/mtk-dramc.c
> > @@ -0,0 +1,232 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2025 MediaTek Inc.
> > + */
> > +#include <linux/bitops.h>
> > +#include <linux/bitfield.h>
> > +#include <linux/device.h>
> > +#include <linux/io.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/printk.h>
> > +
> > +static unsigned int read_reg_field(void __iomem *base, unsigned
> > int offset, unsigned int mask)
>
> Please move this function to before mtk_dramc_probe()
Ok, it will be updated in the next version.
>
> > +{
> > + unsigned int val = readl(base + offset);
> > + unsigned int shift = __ffs(mask);
> > +
> > + return (val & mask) >> shift;
> > +}
> > +
> > +struct mtk_dramc_pdata {
> > + u8 fmeter_version;
> > + u8 ref_freq_mhz;
> > + const u16 *regs;
> > + const u32 *masks;
> > + u32 posdiv_purify;
> > + u8 prediv;
> > + u16 shuffle_offset;
> > +};
> > +
> > +struct mtk_dramc_dev_t {
>
> That may be confused with a typedef so, please, just "struct
> mtk_dramc"
>
Ok, it will be updated in the next version.
> > + void __iomem *anaphy_base;
> > + void __iomem *ddrphy_base;
> > + const struct mtk_dramc_pdata *pdata;
> > +};
> > +
> > +enum mtk_dramc_reg_index {
> > + DRAMC_DPHY_DVFS_STA,
> > + DRAMC_APHY_SHU_PHYPLL2,
> > + DRAMC_APHY_SHU_CLRPLL2,
> > + DRAMC_APHY_SHU_PHYPLL3,
> > + DRAMC_APHY_SHU_CLRPLL3,
> > + DRAMC_APHY_SHU_PHYPLL4,
> > + DRAMC_APHY_ARPI0,
> > + DRAMC_APHY_CA_ARDLL1,
> > + DRAMC_APHY_B0_TX0,
> > +};
> > +
> > +enum mtk_dramc_mask_index {
> > + DRAMC_DPHY_DVFS_SHU_LV,
> > + DRAMC_DPHY_DVFS_PLL_SEL,
> > + DRAMC_APHY_PLL2_SDMPCW,
> > + DRAMC_APHY_PLL3_POSDIV,
> > + DRAMC_APHY_PLL4_FBKSEL,
> > + DRAMC_APHY_ARPI0_SOPEN,
> > + DRAMC_APHY_ARDLL1_CK_EN,
> > + DRAMC_APHY_B0_TX0_SER_MODE,
> > +};
> > +
> > +static const u16 mtk_dramc_regs_mt8196[] = {
> > + [DRAMC_DPHY_DVFS_STA] = 0xe98,
> > + [DRAMC_APHY_SHU_PHYPLL2] = 0x908,
> > + [DRAMC_APHY_SHU_CLRPLL2] = 0x928,
> > + [DRAMC_APHY_SHU_PHYPLL3] = 0x90c,
> > + [DRAMC_APHY_SHU_CLRPLL3] = 0x92c,
> > + [DRAMC_APHY_SHU_PHYPLL4] = 0x910,
> > + [DRAMC_APHY_ARPI0] = 0x0d94,
> > + [DRAMC_APHY_CA_ARDLL1] = 0x0d08,
> > + [DRAMC_APHY_B0_TX0] = 0x0dc4,
> > +};
> > +
> > +static const u32 mtk_dramc_masks_mt8196[] = {
> > + [DRAMC_DPHY_DVFS_SHU_LV] = GENMASK(15, 14),
> > + [DRAMC_DPHY_DVFS_PLL_SEL] = GENMASK(25, 25),
> > + [DRAMC_APHY_PLL2_SDMPCW] = GENMASK(18, 3),
> > + [DRAMC_APHY_PLL3_POSDIV] = GENMASK(13, 11),
> > + [DRAMC_APHY_PLL4_FBKSEL] = GENMASK(6, 6),
> > + [DRAMC_APHY_ARPI0_SOPEN] = GENMASK(26, 26),
> > + [DRAMC_APHY_ARDLL1_CK_EN] = GENMASK(0, 0),
> > + [DRAMC_APHY_B0_TX0_SER_MODE] = GENMASK(4, 3),
> > +};
> > +
>
> function read_reg_field goes here.
>
Got it, thanks.
> > +static int mtk_dramc_probe(struct platform_device *pdev)
> > +{
> > + struct mtk_dramc_dev_t *dramc;
> > + const struct mtk_dramc_pdata *pdata;
> > +
> > + dramc = devm_kzalloc(&pdev->dev, sizeof(struct
> > mtk_dramc_dev_t), GFP_KERNEL);
> > + if (!dramc)
> > + return dev_err_probe(&pdev->dev, -ENOMEM, "Failed to
> > allocate memory\n");
> > +
> > + pdata = of_device_get_match_data(&pdev->dev);
> > + if (!pdata)
> > + return dev_err_probe(&pdev->dev, -EINVAL, "No
> > platform data available\n");
> > +
> > + dramc->pdata = pdata;
> > +
> > + dramc->anaphy_base = devm_platform_ioremap_resource(pdev, 0);
> > + if (IS_ERR(dramc->anaphy_base))
> > + return dev_err_probe(&pdev->dev, PTR_ERR(dramc-
> > >anaphy_base),
> > + "Unable to map ANAPHY base\n");
> > +
> > + dramc->ddrphy_base = devm_platform_ioremap_resource(pdev, 1);
> > + if (IS_ERR(dramc->ddrphy_base))
> > + return dev_err_probe(&pdev->dev, PTR_ERR(dramc-
> > >ddrphy_base),
> > + "Unable to map DDRPHY base\n");
> > +
> > + platform_set_drvdata(pdev, dramc);
> > + return 0;
> > +}
> > +
> > +static unsigned int mtk_fmeter_v1(struct mtk_dramc_dev_t *dramc)
> > +{
> > + const struct mtk_dramc_pdata *pdata = dramc->pdata;
> > + unsigned int shu_level, pll_sel, offset;
> > + unsigned int sdmpcw, posdiv, clkdiv, fbksel, sopen, async_ca,
> > ser_mode;
> > + unsigned int prediv_freq, posdiv_freq, vco_freq;
> > + unsigned int final_rate;
> > +
> > + shu_level = read_reg_field(dramc->ddrphy_base, pdata-
> > >regs[DRAMC_DPHY_DVFS_STA],
> > + pdata-
> > >masks[DRAMC_DPHY_DVFS_SHU_LV]);
> > + pll_sel = read_reg_field(dramc->ddrphy_base, pdata-
> > >regs[DRAMC_DPHY_DVFS_STA],
> > + pdata-
> > >masks[DRAMC_DPHY_DVFS_PLL_SEL]);
> > + offset = pdata->shuffle_offset * shu_level;
> > +
> > + sdmpcw = read_reg_field(dramc->anaphy_base,
> > + ((pll_sel == 0) ?
> > + pdata->regs[DRAMC_APHY_SHU_PHYPLL2] :
> > + pdata->regs[DRAMC_APHY_SHU_CLRPLL2])
> > + offset,
> > + pdata-
> > >masks[DRAMC_APHY_PLL2_SDMPCW]);
> > + posdiv = read_reg_field(dramc->anaphy_base,
> > + ((pll_sel == 0) ?
> > + pdata->regs[DRAMC_APHY_SHU_PHYPLL3] :
> > + pdata->regs[DRAMC_APHY_SHU_CLRPLL3])
> > + offset,
> > + pdata-
> > >masks[DRAMC_APHY_PLL3_POSDIV]);
> > + fbksel = read_reg_field(dramc->anaphy_base, pdata-
> > >regs[DRAMC_APHY_SHU_PHYPLL4] + offset,
> > + pdata-
> > >masks[DRAMC_APHY_PLL4_FBKSEL]);
> > + sopen = read_reg_field(dramc->anaphy_base, pdata-
> > >regs[DRAMC_APHY_ARPI0] + offset,
> > + pdata->masks[DRAMC_APHY_ARPI0_SOPEN]);
> > + async_ca = read_reg_field(dramc->anaphy_base, pdata-
> > >regs[DRAMC_APHY_CA_ARDLL1] + offset,
> > + pdata-
> > >masks[DRAMC_APHY_ARDLL1_CK_EN]);
> > + ser_mode = read_reg_field(dramc->anaphy_base, pdata-
> > >regs[DRAMC_APHY_B0_TX0] + offset,
> > + pdata-
> > >masks[DRAMC_APHY_B0_TX0_SER_MODE]);
> > +
> > + clkdiv = (ser_mode == 1) ? 1 : 0;
> > + posdiv &= ~(pdata->posdiv_purify);
> > +
> > + prediv_freq = pdata->ref_freq_mhz * (sdmpcw >> pdata-
> > >prediv);
> > + posdiv_freq = (prediv_freq >> posdiv) >> 1;
> > + vco_freq = posdiv_freq << fbksel;
> > + final_rate = vco_freq >> clkdiv;
> > +
> > + if (sopen == 1 && async_ca == 1)
> > + final_rate >>= 1;
> > +
> > + return final_rate;
> > +}
> > +
> > +/*
>
> You're so near to kerneldoc that you might just as well use it.
>
Ok, I will update the comments in the next version.
> /**
> * mtk_dramc_get_data_rate - Calculate DRAM data rate
> * @dev - Device pointer
> *
> * Return: DRAM Data Rate in MB/s or negative number for error
> */
>
> > + * mtk_dramc_get_data_rate - calculate DRAM data rate
> > + *
> > + * Returns DRAM data rate (MB/s)
> > + */
> > +static unsigned int mtk_dramc_get_data_rate(struct device *dev)
> > +{
> > + struct mtk_dramc_dev_t *dramc_dev = dev_get_drvdata(dev);
> > +
> > + if (!dramc_dev) {
> > + dev_err(dev, "DRAMC device data not found\n");
>
> That can't happen, because you're assigning drvdata in the probe
> function
>
> > + return -EINVAL;
> > + }
> > +
> > + if (dramc_dev->pdata) {
> > + if (dramc_dev->pdata->fmeter_version == 1)
> > + return mtk_fmeter_v1(dramc_dev);
> > +
> > + dev_err(dev, "Unsupported fmeter version\n");
> > + return -EINVAL;
> > + }
> > + dev_err(dev, "DRAMC platform data not found\n");
>
> That also can't happen.
>
> > + return -EINVAL;
> > +}
>
> /**
> * mtk_dramc_get_data_rate - Calculate DRAM data rate
> * @dev - Device pointer
> *
> * Return: DRAM Data Rate in MB/s or negative number for error
> */
> static unsigned int mtk_dramc_get_data_rate(struct device *dev)
> {
> struct mtk_dramc *dramc = dev_get_drvdata(dev);
>
> if (dramc_dev->pdata->fmeter_version == 1)
> return mtk_fmeter_v1(dramc_dev);
>
> dev_err(dev, "Frequency meter version %u not supported\n");
> return -EINVAL;
> };
>
Thanks for the reminder, this part will be updated in the next version.
> > +
> > +static ssize_t dram_data_rate_show(struct device *dev,
> > + struct device_attribute *attr,
> > char *buf)
> > +{
> > + return snprintf(buf, PAGE_SIZE, "DRAM data rate = %u\n",
> > + mtk_dramc_get_data_rate(dev));
> > +}
> > +
> > +static DEVICE_ATTR_RO(dram_data_rate);
> > +
> > +static struct attribute *mtk_dramc_attrs[] = {
> > + &dev_attr_dram_data_rate.attr,
> > + NULL
> > +};
> > +ATTRIBUTE_GROUPS(mtk_dramc);
> > +
> > +static const struct mtk_dramc_pdata dramc_pdata_mt8196 = {
> > + .fmeter_version = 1,
> > + .ref_freq_mhz = 26,
> > + .regs = mtk_dramc_regs_mt8196,
> > + .masks = mtk_dramc_masks_mt8196,
> > + .posdiv_purify = BIT(2),
> > + .prediv = 7,
> > + .shuffle_offset = 0x700,
> > +};
> > +
> > +static const struct of_device_id mtk_dramc_of_ids[] = {
> > + { .compatible = "mediatek,mt8196-dramc", .data =
> > &dramc_pdata_mt8196 },
> > + {}
>
> { /* sentinel */ }
>
> > +};
> > +MODULE_DEVICE_TABLE(of, mtk_dramc_of_ids);
> > +
> > +static struct platform_driver mtk_dramc_driver = {
> > + .probe = mtk_dramc_probe,
> > + .driver = {
> > + .name = "mtk_dramc_drv",
>
> .name = "mtk-dramc"
>
> > + .of_match_table = mtk_dramc_of_ids,
> > + .dev_groups = mtk_dramc_groups,
> > + },
> > +};
> > +
>
> No blank line here:
>
> };
> module_platform_driver(....)
>
> I think that v4 will be the final version :-)
>
> Cheers,
> Angelo
>
Thanks for your suggestions. I will make updates based on the above
comments in the next version.
Best regards,
Crystal
> > +module_platform_driver(mtk_dramc_driver);
> > +
> > +MODULE_AUTHOR("Crystal Guo <crystal.guo@...iatek.com>");
> > +MODULE_DESCRIPTION("MediaTek DRAM Controller Driver");
> > +MODULE_LICENSE("GPL");
>
>
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