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Message-ID: <4bad42c867a838da413154fa0a779547d642642c.camel@mediatek.com>
Date: Wed, 2 Apr 2025 03:51:41 +0000
From: Crystal Guo (郭晶) <Crystal.Guo@...iatek.com>
To: "robh@...nel.org" <robh@...nel.org>, "matthias.bgg@...il.com"
<matthias.bgg@...il.com>, AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>, "krzk@...nel.org"
<krzk@...nel.org>, "conor+dt@...nel.org" <conor+dt@...nel.org>
CC: "linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>, "linux-kernel@...r.kernel.org"
<linux-kernel@...r.kernel.org>, "linux-mediatek@...ts.infradead.org"
<linux-mediatek@...ts.infradead.org>, "devicetree@...r.kernel.org"
<devicetree@...r.kernel.org>, Project_Global_Chrome_Upstream_Group
<Project_Global_Chrome_Upstream_Group@...iatek.com>
Subject: Re: [v3,1/2] dt-bindings: memory-controllers: Add MediaTek DRAM
controller interface
On Wed, 2025-03-26 at 11:18 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>
>
> Il 26/03/25 07:30, Crystal Guo ha scritto:
> > A MediaTek DRAM controller interface to provide the current DDR
> > data rate.
> >
> > Signed-off-by: Crystal Guo <crystal.guo@...iatek.com>
> > ---
> > .../memory-controllers/mediatek,dramc.yaml | 44
> > +++++++++++++++++++
> > 1 file changed, 44 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/memory-
> > controllers/mediatek,dramc.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/memory-
> > controllers/mediatek,dramc.yaml
> > b/Documentation/devicetree/bindings/memory-
> > controllers/mediatek,dramc.yaml
> > new file mode 100644
> > index 000000000000..8bdacfc36cb5
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/memory-
> > controllers/mediatek,dramc.yaml
>
> The filename should be "mediatek,mt8196-dramc.yaml"
>
For other MediaTek SOCs, the method of calculating current ddr data
rate is similar to that of MT8196. After changing "mediatek,dramc.yaml"
to "mediatek,mt8196-dramc.yaml", would future Mediatek SOCs need to add
a separate yaml file again? or could they reuse mediatek,mt8196-
dramc.yaml? Thank you for your guidance.
Best regards,
Crystal
>
> > @@ -0,0 +1,44 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +# Copyright (c) 2025 MediaTek Inc.
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/memory-controllers/mediatek,dramc.yaml*__;Iw!!CTRNKA9wMg0ARbw!gH5hMTJ34ZcYfNMfLUNL-dH9SMyQGr06kJ4jij1anezByF7IBOSbkYNdqysgHoz-rSRNwM9r6RaaTC1MO2882ojif26oaBzg$
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!gH5hMTJ34ZcYfNMfLUNL-dH9SMyQGr06kJ4jij1anezByF7IBOSbkYNdqysgHoz-rSRNwM9r6RaaTC1MO2882ojifw8f6sUH$
> > +
> > +title: MediaTek DRAM Controller (DRAMC)
> > +
> > +maintainers:
> > + - Crystal Guo <crystal.guo@...iatek.com>
> > +
> > +description:
> > + A MediaTek DRAM controller interface to provide the current data
> > rate of DRAM.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - mediatek,mt8196-dramc
>
> P.S.: bindings maintainers: this driver is expected to get more
> compatibles soon.
>
> Cheers,
> Angelo
>
>
> > +
> > + reg:
> > + items:
> > + - description: anaphy registers
> > + - description: ddrphy registers
> > +
> > +additionalProperties: false
> > +
> > +required:
> > + - compatible
> > + - reg
> > +
> > +examples:
> > + - |
> > + soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + memory-controller@...36000 {
> > + compatible = "mediatek,mt8196-dramc";
> > + reg = <0 0x10236000 0 0x2000>,
> > + <0 0x10238000 0 0x2000>;
> > + };
> > + };
>
>
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