linux-kernel - [PATCH v2 3/5] arm64: dts: ti: k3-j7200: Add PCIe ctrl node to scm

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Message-ID: <20250402113201.151195-4-j-choudhary@ti.com>
Date: Wed, 2 Apr 2025 17:01:59 +0530
From: Jayesh Choudhary <j-choudhary@...com>
To: <robh@...nel.org>, <krzk+dt@...nel.org>, <conor+dt@...nel.org>,
        <nm@...com>, <vigneshr@...com>, <afd@...com>, <s-vadapalli@...com>,
        <linux-kernel@...r.kernel.org>
CC: <kristo@...nel.org>, <rogerq@...nel.org>, <kishon@...nel.org>,
        <devicetree@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
        <j-choudhary@...com>
Subject: [PATCH v2 3/5] arm64: dts: ti: k3-j7200: Add PCIe ctrl node to scm_conf region

From: Andrew Davis <afd@...com>

This region is used for controlling the function of the PCIe IP. It is
compatible with "ti,j784s4-pcie-ctrl", add this here and use it with
the PCIe node.

Signed-off-by: Andrew Davis <afd@...com>
[j-choudhary@...com: Add changes to k3-j7200-evm-pcie1-ep.dtso]
Signed-off-by: Jayesh Choudhary <j-choudhary@...com>
---
 arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso | 2 +-
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi         | 7 ++++++-
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso b/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso
index 3cc315a0e084..281076d905f3 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso
+++ b/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso
@@ -48,6 +48,6 @@ pcie1_ep: pcie-ep@...0000 {
 		dma-coherent;
 		phys = <&serdes0_pcie_link>;
 		phy-names = "pcie-phy";
-		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
+		ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
 	};
 };
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 5ab510a0605f..dbb000657377 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -32,6 +32,11 @@ scm_conf: scm-conf@...000 {
 		#size-cells = <1>;
 		ranges = <0x00 0x00 0x00100000 0x1c000>;
 
+		pcie1_ctrl: pcie-ctrl@...4 {
+			compatible = "ti,j784s4-pcie-ctrl", "syscon";
+			reg = <0x4074 0x4>;
+		};
+
 		serdes_ln_ctrl: mux-controller@...0 {
 			compatible = "reg-mux";
 			reg = <0x4080 0x20>;
@@ -764,7 +769,7 @@ pcie1_rc: pcie@...0000 {
 		interrupt-names = "link_state";
 		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
 		device_type = "pci";
-		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
+		ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
 		max-link-speed = <3>;
 		num-lanes = <4>;
 		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
-- 
2.34.1