linux-kernel - Re: [External] Re: [PATCH] iommu: riscv: Split 8-byte accesses on 32 bit I/O bus platform

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Message-ID: <CAPYmKFtOV6JfAudcw4gfWpgQv8k3Q6dNrTynqYo2tSdZEAwKHA@mail.gmail.com>
Date: Wed, 2 Apr 2025 20:20:04 +0800
From: Xu Lu <luxu.kernel@...edance.com>
To: David Laight <david.laight.linux@...il.com>
Cc: Jason Gunthorpe <jgg@...pe.ca>, Jessica Clarke <jrtc27@...c27.com>, tjeznach@...osinc.com, 
	joro@...tes.org, will@...nel.org, robin.murphy@....com, alex@...ti.fr, 
	lihangjing@...edance.com, xieyongji@...edance.com, 
	linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org, 
	iommu@...ts.linux.dev
Subject: Re: [External] Re: [PATCH] iommu: riscv: Split 8-byte accesses on 32
 bit I/O bus platform

Hi David,

All these 64 bit registers are updated during initialization (when
allocating page table and iommu queues) and destruction (when
disabling interrupts and iommu queues) in the existing iommu driver.
There won't be multiple cpu operating simultaneously.

Some 64 bit pmu registers are also updated during pmu event
initialization and overflow handling in the oncoming iommu pmu
driver[1]. There will also be no concurrency issues due to the pmu
framework unless the ACPI/DTS is misconfigured and two iommus get the
same register resources.

So maybe a lock is not necessary. Please correct me if I missed anything.

[1] https://lore.kernel.org/all/20250115030306.29735-1-zong.li@sifive.com/

Best regards,
Xu Lu

On Wed, Apr 2, 2025 at 5:02 AM David Laight
<david.laight.linux@...il.com> wrote:
>
> On Tue, 1 Apr 2025 12:44:12 -0300
> Jason Gunthorpe <jgg@...pe.ca> wrote:
>
> > On Wed, Mar 26, 2025 at 11:26:07AM +0800, Xu Lu wrote:
> > > Hi Jessica,
> > >
> > > > Is such a platform conformant to the specification?
> > >
> > > We have talked about this before [1]. I think the IOMMU spec does not
> > > mandate the implementation of 8-byte access functionality. The related
> > > sentences are listed below:
> > >
> > > "The 8-byte IOMMU registers are defined in such a way that software
> > > can perform two individual 4-byte accesses, or hardware can perform
> > > two independent 4-byte transactions resulting from an 8-byte access,
> > > to the high and low halves of the register, in that order, as long as
> > > the register semantics, with regard to side-effects, are respected
> > > between the two software accesses, or two hardware transactions,
> > > respectively."
> >
> > I think the commit message should explain an anyalsis that the code is
> > safe against the mentioned side effects due to ordering.
> >
> > And a comment should explain this:
> >
> > +#define riscv_iommu_writeq(iommu, addr, val) \
> > +       ((addr == RISCV_IOMMU_REG_IOHPMCYCLES) ? \
> > +        lo_hi_writeq_relaxed((val), (iommu)->reg + (addr)) : \
> > +        hi_lo_writeq_relaxed((val), (iommu)->reg + (addr)))
> >
> > As the naive reading of the above spec paragraph doesn't seem like
> > there are exceptions or why one register has to be the opposite order.
> >
> > Also missing () around addr
>
> It is also double-evaluating (addr).
>
> I hope there is a lock, interleaved accesses from multiple cpu
> may not work.



>
>         David
>
> >
> > Jason
> >
>