Message-ID: <59c41c52-25f3-5506-a70f-9275425a629f@oss.nxp.com>
Date: Thu, 3 Apr 2025 08:27:54 +0300
From: Ghennadi Procopciuc <ghennadi.procopciuc@....nxp.com>
To: Daniel Lezcano <daniel.lezcano@...aro.org>, tglx@...utronix.de
Cc: linux-kernel@...r.kernel.org, thomas.fossati@...aro.org,
 Larisa.Grigore@....com, ghennadi.procopciuc@....com,
 krzysztof.kozlowski@...aro.org, S32@....com,
 Maxime Coquelin <mcoquelin.stm32@...il.com>,
 Alexandre Torgue <alexandre.torgue@...s.st.com>,
 "moderated list:ARM/STM32 ARCHITECTURE"
 <linux-stm32@...md-mailman.stormreply.com>,
 "moderated list:ARM/STM32 ARCHITECTURE"
 <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v4 2/2] clocksource/drivers/nxp-timer: Add the System
 Timer Module for the s32gx platforms

On 4/2/2025 12:07 PM, Daniel Lezcano wrote:
> STM supports commonly required system and application software timing
> functions. STM includes a 32-bit count-up timer and four 32-bit
> compare channels with a separate interrupt source for each
> channel. The timer is driven by the STM module clock divided by an
> 8-bit prescale value (1 to 256).
> 
> STM has the following features:
>     • One 32-bit count-up timer with an 8-bit prescaler
>     • Four 32-bit compare channels
>     • An independent interrupt source for each channel
>     • Ability to stop the timer in Debug mode
> 
> The s32g platform is declined into two versions, the s32g2 and the
> s32g3. The former has a STM block with 8 timers and the latter has 12
> timers.
> 
> The platform is designed to have one usable STM instance per core on
> the system which is composed of 3 x Cortex-M3 + 4 Cortex-A53 for the
> s32g2 and 3 x Cortex-M3 + 8 Cortex-A53 for the s32g3.
> 
> There is a special STM instance called STM_TS which is dedicated to
> the timestamp. The 7th STM instance STM_07 is directly tied to the
> STM_TS which means it is not usable as a clockevent.
> 
> The driver instantiate each STM described in the device tree as a

nitpick: instantiate -> instantiates

> clocksource and a clockevent conforming to the reference manual even
> if the Linux system does not use all of the clocksource. Each
> clockevent will have a cpumask set for a specific CPU.
> 
> Given the counter is shared between the clocksource and the
> clockevent, the STM module can not be disabled by one or another so
> the refcounting mechanism is used to stop the counter when it reaches
> zero and to start it when it is one. The suspend and resume relies on

nitpick: relies -> rely

> the refcount to stop the module.
> 
> As the device tree will have multiple STM entries, the driver can be
> probed in parallel with the async option but it is not enabled
> yet. However, the driver code takes care of preventing a race by
> putting a lock to protect the number of STM instances global variable
> which means it is ready to support the option when enough testing will
> be done with the underlying time framework.
> 
> Cc: Ghennadi Procopciuc <ghennadi.procopciuc@....nxp.com>
> Cc: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> Cc: Thomas Fossati <thomas.fossati@...aro.org>
> Suggested-by: Ghennadi Procopciuc <ghennadi.procopciuc@....com>
> Signed-off-by: Daniel Lezcano <daniel.lezcano@...aro.org>
> ---
>  drivers/clocksource/Kconfig         |   9 +
>  drivers/clocksource/Makefile        |   2 +
>  drivers/clocksource/timer-nxp-stm.c | 495 ++++++++++++++++++++++++++++
>  3 files changed, 506 insertions(+)
>  create mode 100644 drivers/clocksource/timer-nxp-stm.c
> 
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index 487c85259967..e86e327392af 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -763,4 +763,13 @@ config RALINK_TIMER
>  	  Enables support for system tick counter present on
>  	  Ralink SoCs RT3352 and MT7620.
>  
> +config NXP_STM_TIMER
> +	bool "NXP System Timer Module driver"
> +	depends on ARCH_S32 || COMPILE_TEST
> +	select CLKSRC_MMIO
> +	help
> +	  Support for NXP System Timer Module. It will create, in this
> +	  order, a clocksource, a broadcast clockevent and a per cpu
> +	  clockevent.

Is this description accurate? Will a broadcast event be created?

[ ... ]
> +
> +static int nxp_stm_clockevent_set_next_event(unsigned long delta, struct clock_event_device *ced)
> +{
> +	struct stm_timer *stm_timer = ced_to_stm(ced);
> +	u32 val;
> +
> +	nxp_stm_clockevent_disable(stm_timer);
> +
> +	stm_timer->delta = delta;
> +
> +	val = nxp_stm_clockevent_read_counter(stm_timer) + delta;
> +
> +	writel(val, STM_CMP0(stm_timer->base));
> +
> +	/*
> +	 * The counter is shared across the channels and can not be
> +	 * stopped while we are setting the next event. If the delta
> +	 * is very small it is possible the counter increases above
> +	 * the computed 'val'. The min_delta value specified when
> +	 * registering the clockevent will prevent that. The second
> +	 * case is if the counter wraps while we compute the 'val' and
> +	 * before writing the comparator register. We read the counter,
> +	 * check if we are back in time and abort the timer with -ETIME.
> +	 */
> +	if (val > nxp_stm_clockevent_read_counter(stm_timer) + delta)
> +		return -ETIME;

In my opinion, there is still a race condition between the running
counter and the nxp_stm_clockevent_enable function. This means that the
counter may wrap around between the 'val >
nxp_stm_clockevent_read_counter(stm_timer) + delta' check and the actual
instruction part of the nxp_stm_clockevent_enable that enables the
interrupt. Moreover, this implementation seems to prohibit the case when
the value of val results after a wrap-around of the counter, which seems
like an artificial constraint to me.

In my view, the goal here is to identify the cases when the timer fires
while the comparator interrupt is disabled. There would be too many
cases to consider if using u32 only to store the current value of the
counter and the one to be written in the comparator. Therefore, to
simplify the implementation, I would work with u64. Here is the proposal
(not tested):

u64 val, ctime;

nxp_stm_clockevent_disable(stm_timer);

ctime = nxp_stm_clockevent_read_counter(stm_timer);

/* Build the targeted time using u64, which is not impacted by wraps
since both added values are u32 */
val = ctime + delta;

/* Ensure we have enough time to set up the interrupt without generating
a false one */
writel(lower_32_bits(ctime) - 1, STM_CMP0(stm_timer->base));

nxp_stm_clockevent_enable(stm_timer);

ctime = nxp_stm_clockevent_read_counter(stm_timer);

/* The delta has already passed */
if (ctime > lower_32_bits(val)) {
    nxp_stm_clockevent_disable(stm_timer);
    return -ETIME;
}

/* Keep the 32 LSB bits of the val */
writel(lower_32_bits(val), STM_CMP0(stm_timer->base));


[ ... ]
> +static irqreturn_t nxp_stm_module_interrupt(int irq, void *dev_id)
> +{
> +	struct stm_timer *stm_timer = dev_id;
> +	struct clock_event_device *ced = &stm_timer->ced;
> +	u32 val;
> +
> +	/*
> +	 * The interrupt is shared across the channels in the
> +	 * module. But this one is configured to run only one channel,
> +	 * consequently it is pointless to test the interrupt flags
> +	 * before and we can directly reset the channel 0 irq flag
> +	 * register.
> +	 */
> +	writel(STM_CIR_CIF, STM_CIR0(stm_timer->base));
> +
> +	/*
> +	 * Update STM_CMP value using the counter value
> +	 */
> +	val = nxp_stm_clockevent_read_counter(stm_timer) + stm_timer->delta;
> +
> +	writel(val, STM_CMP0(stm_timer->base));
> +
> +	/*
> +	 * stm hardware doesn't support oneshot, it will generate an
> +	 * interrupt and start the counter again so software need to

nitpick: software need -> software needs

> +	 * disable the timer to stop the counter loop in ONESHOT mode.
> +	 */
> +	if (likely(clockevent_state_oneshot(ced)))
> +		nxp_stm_clockevent_disable(stm_timer);
> +
> +	ced->event_handler(ced);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static int __init nxp_stm_timer_probe(struct platform_device *pdev)
> +{
> +	struct stm_timer *stm_timer;
> +	struct device *dev = &pdev->dev;
> +	struct device_node *np = dev->of_node;
> +	const char *name = of_node_full_name(np);
> +	struct clk *clk;
> +	void __iomem *base;
> +	int irq, ret;
> +
> +	/*
> +	 * The device tree can have multiple STM nodes described, so
> +	 * it makes this driver a good candidate for the async probe.
> +	 * It is still unclear if the time framework does correctly
> +	 * handle a parallel loading of the timers but at least this

nitpick: does correctly handle a parallel loading -> correctly handles
parallel loading

> +	 * driver is ready to support the option.
> +	 */
> +	guard(stm_instances)(&stm_instances_lock);
> +
> +	/*
> +	 * The S32Gx are SoCs featuring a diverse set of cores. Linux
> +	 * is expected to run on Cortex-A53 cores, while other
> +	 * software stacks will operate on Cortex-M cores. The number
> +	 * of STM instances has been sized to include at most one
> +	 * instance per core.
> +	 *
> +	 * As we need a clocksource and a clockevent per cpu, we
> +	 * simply initialize a clocksource per cpu along with the
> +	 * clockevent which makes the resulting code simpler.
> +	 *
> +	 * However if the device tree is describing more STM instances
> +	 * than the number of cores, then we ignore them.
> +	 */
> +	if (stm_instances >= num_possible_cpus())
> +		return 0;
> +
> +	base = devm_of_iomap(dev, np, 0, NULL);
> +	if (IS_ERR(base))
> +		return dev_err_probe(dev, PTR_ERR(base), "Failed to iomap %pOFn\n", np);
> +
> +	irq = platform_get_irq(pdev, 0);
> +	if (irq < 0)
> +		return dev_err_probe(dev, irq, "Failed to get IRQ\n");
> +
> +	clk = devm_clk_get_enabled(dev, NULL);
> +	if (IS_ERR(clk))
> +		return dev_err_probe(dev, PTR_ERR(clk), "Clock not found\n");
> +
> +	stm_timer = devm_kzalloc(dev, sizeof(*stm_timer), GFP_KERNEL);
> +	if (!stm_timer)
> +		return -ENOMEM;
> +
> +	ret = devm_request_irq(dev, irq, nxp_stm_module_interrupt,
> +			       IRQF_TIMER | IRQF_NOBALANCING, name, stm_timer);
> +	if (ret)
> +		return dev_err_probe(dev, ret, "Unable to allocate interrupt line\n");
> +
> +	ret = nxp_stm_clocksource_init(dev, stm_timer, name, base, clk);
> +	if (ret)
> +		return ret;
> +
> +	/*
> +	 * Next probed STM will be a per CPU clockevent, until
> +	 * we probe as much as we have CPUs available on the

nitpick: as much -> as many

> +	 * system, we do a partial initialization
> +	 */
> +	ret = nxp_stm_clockevent_per_cpu_init(dev, stm_timer, name,
> +					      base, irq, clk,
> +					      stm_instances);
> +	if (ret)
> +		return ret;
> +
> +	stm_instances++;
> +
> +	/*
> +	 * The number of probed STM for per CPU clockevent is

nitpick: STM -> STMs

> +	 * equal to the number of available CPUs on the
> +	 * system. We install the cpu hotplug to finish the
> +	 * initialization by registering the clockevents
> +	 */
> +	if (stm_instances == num_possible_cpus()) {
> +		ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "STM timer:starting",
> +					nxp_stm_clockevent_starting_cpu, NULL);
> +		if (ret < 0)
> +			return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id nxp_stm_of_match[] = {
> +	{ .compatible = "nxp,s32g2-stm" },
> +	{ }
> +};
> +MODULE_DEVICE_TABLE(of, nxp_stm_of_match);
> +
> +static struct platform_driver nxp_stm_probe = {
> +	.probe	= nxp_stm_timer_probe,
> +	.driver	= {
> +		.name		= "nxp-stm",
> +		.of_match_table	= nxp_stm_of_match,
> +	},
> +};
> +module_platform_driver(nxp_stm_probe);
> +
> +MODULE_DESCRIPTION("NXP System Timer Module driver");
> +MODULE_LICENSE("GPL");

-- 
Regards,
Ghennadi

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