linux-kernel - [PATCH] wifi: ath12k: Fix misspelling "upto" in dp.c

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Message-Id: <20250407-upto-v1-1-23ca65f2ccdf@oss.qualcomm.com>
Date: Mon, 07 Apr 2025 11:28:26 -0700
From: Jeff Johnson <jeff.johnson@....qualcomm.com>
To: Johannes Berg <johannes@...solutions.net>,
        Jeff Johnson <jjohnson@...nel.org>
Cc: linux-wireless@...r.kernel.org, ath12k@...ts.infradead.org,
        linux-kernel@...r.kernel.org,
        Jeff Johnson <jeff.johnson@....qualcomm.com>
Subject: [PATCH] wifi: ath12k: Fix misspelling "upto" in dp.c

ath12k-check is flagging:

drivers/net/wireless/ath/ath12k/dp.c:1656: 'upto' may be misspelled - perhaps 'up to'?

Replace "upto" with "up to" and split the comment line so that it
doesn't exceed 80 columns.

Signed-off-by: Jeff Johnson <jeff.johnson@....qualcomm.com>
---
To be honest, I saw this when I was processing the original patch, but
I thought this was just in the commit text and let it slide. But now
that I see it is in the code, I'm fixing it.
---
 drivers/net/wireless/ath/ath12k/dp.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/wireless/ath/ath12k/dp.c b/drivers/net/wireless/ath/ath12k/dp.c
index 80b9f4594dee..59f61341383a 100644
--- a/drivers/net/wireless/ath/ath12k/dp.c
+++ b/drivers/net/wireless/ath/ath12k/dp.c
@@ -1653,7 +1653,8 @@ static int ath12k_dp_reoq_lut_setup(struct ath12k_base *ab)
 
 	/* Bits in the register have address [39:8] LUT base address to be
 	 * allocated such that LSBs are assumed to be zero. Also, current
-	 * design supports paddr upto 4 GB max hence it fits in 32 bit register only
+	 * design supports paddr up to 4 GB max hence it fits in 32 bit
+	 * register only
 	 */
 
 	ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_LUT_BASE0(ab),

---
base-commit: 4bcceba241524d8d52bdadf216f9f894e394fcde
change-id: 20250407-upto-a76497324734