linux-kernel - [PATCH 5/9] dt-bindings: timer: add Andes machine timer

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Message-ID: <20250407104937.315783-6-ben717@andestech.com>
Date: Mon, 7 Apr 2025 18:49:33 +0800
From: Ben Zong-You Xie <ben717@...estech.com>
To: <devicetree@...r.kernel.org>, <linux-riscv@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>
CC: <paul.walmsley@...ive.com>, <palmer@...belt.com>, <aou@...s.berkeley.edu>,
        <alex@...ti.fr>, <robh@...nel.org>, <krzk+dt@...nel.org>,
        <conor+dt@...nel.org>, <tglx@...utronix.de>,
        <daniel.lezcano@...aro.org>, <prabhakar.mahadev-lad.rj@...renesas.com>,
        <tim609@...estech.com>, "Ben
 Zong-You Xie" <ben717@...estech.com>
Subject: [PATCH 5/9] dt-bindings: timer: add Andes machine timer

Add the DT binding documentation for Andes machine timer.

The RISC-V architecture defines a machine timer that provides a real-time
counter and generates timer interrupts. Andes machiner timer (PLMT0) is
the implementation of the machine timer, and it contains memory-mapped
registers (mtime and mtimecmp). This device supports up to 32 cores.

Signed-off-by: Ben Zong-You Xie <ben717@...estech.com>
---
 .../bindings/timer/andestech,plmt0.yaml       | 42 +++++++++++++++++++
 MAINTAINERS                                   |  1 +
 2 files changed, 43 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/andestech,plmt0.yaml

diff --git a/Documentation/devicetree/bindings/timer/andestech,plmt0.yaml b/Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
new file mode 100644
index 000000000000..e0ea3ce86b76
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/andestech,plmt0.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Andes machine timer
+
+maintainers:
+  - Ben Zong-You Xie <ben717@...estech.com>
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - andestech,qilai-aclint-mtimer
+      - const: andestech,plmt0
+
+  reg:
+    maxItems: 1
+
+  interrupts-extended:
+    minItems: 1
+    maxItems: 32
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts-extended
+
+examples:
+  - |
+    interrupt-controller@...000 {
+      compatible = "andestech,qilai-aclint-mtimer", "andestech,plmt0";
+      reg = <0x100000 0x100000>;
+      interrupts-extended = <&cpu0intc 7>,
+                            <&cpu1intc 7>,
+                            <&cpu2intc 7>,
+                            <&cpu3intc 7>;
+    };
diff --git a/MAINTAINERS b/MAINTAINERS
index 645d7137cb07..d1e1b98dfe7b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20730,6 +20730,7 @@ M:	Ben Zong-You Xie <ben717@...estech.com>
 S:	Maintained
 F:	Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
 F:	Documentation/devicetree/bindings/riscv/andes.yaml
+F:	Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
 
 RISC-V ARCHITECTURE
 M:	Paul Walmsley <paul.walmsley@...ive.com>
-- 
2.34.1