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Message-ID: <20250408031309.2095-1-zhangxiquan@hisilicon.com>
Date: Tue, 8 Apr 2025 11:13:09 +0800
From: Xiquan Zhang <zhangxiquan@...ilicon.com>
To: <catalin.marinas@....com>, <will@...nel.org>, <corbet@....net>
CC: <linux-arm-kernel@...ts.infradead.org>, <linux-doc@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
Subject: [PATCH] Documentation (arm64):Advanced SIMD and floating point support condition
From: zhangyu <zhangyu550@...wei.com>
Because the kernel code cannot be started from el1
according to the booting.rst.
It is found that CPTR_EL2.FPEN is not configured.
After the configuration, the problem is solved.
Signed-off-by: zhangyu <zhangyu550@...wei.com>
Signed-off-by: zhangxiquan <zhangxiquan@...ilicon.com>
---
Documentation/arch/arm64/booting.rst | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm64/booting.rst
index dee7b6de864f..ccefc42b51bc 100644
--- a/Documentation/arch/arm64/booting.rst
+++ b/Documentation/arch/arm64/booting.rst
@@ -309,6 +309,7 @@ Before jumping into the kernel, the following conditions must be met:
- If EL2 is present and the kernel is entered at EL1:
- CPTR_EL2.TFP (bit 10) must be initialised to 0b0.
+ - CPTR_EL2.FPEN (bit 21:20) must be initialised to 0b11.
For CPUs with the Scalable Vector Extension (FEAT_SVE) present:
--
2.45.1.windows.1
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