linux-kernel - Re: [PATCH v1 0/2] x86/cacheinfo: Fixes for CPUID(0x80000005) and CPUID(0x80000006)

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Message-ID: <Z_Zqkpma-vWgpW3o@lx-t490>
Date: Wed, 9 Apr 2025 14:39:46 +0200
From: "Ahmed S. Darwish" <darwi@...utronix.de>
To: Ingo Molnar <mingo@...nel.org>
Cc: Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
	Dave Hansen <dave.hansen@...ux.intel.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Andrew Cooper <andrew.cooper3@...rix.com>,
	"H. Peter Anvin" <hpa@...or.com>,
	John Ogness <john.ogness@...utronix.de>, x86@...nel.org,
	x86-cpuid@...ts.linux.dev, LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v1 0/2] x86/cacheinfo: Fixes for CPUID(0x80000005) and
 CPUID(0x80000006)

Hi,

On Wed, 09 Apr 2025, Ingo Molnar wrote:
>
> * Ahmed S. Darwish <darwi@...utronix.de> wrote:
>
> > While working on the x86-cpuid-db CPUID model on top of the CPUID(2) and
> > CPUID(4) cleanups at tip/x86/cpu,[*] I've discovered some L1/2/3 cache
> > associativity parsing issues for the AMD CPUID(4) emulation logic .
> >
> > Here are the fixes on top of -rc1.
>
> Could you please send these against tip:master?
>
> tip:x86/cpu already has your previous series, and I don't see the need
> to create a version skew between v6.15 and the x86 tree for v6.16.
>

Sure, I've just sent v2 over tip:master here:

   https://lore.kernel.org/lkml/20250409122233.1058601-1-darwi@linutronix.de

Ironically, this PQ was originally on top of tip:x86/cpu, but I was not
sure if the tip:x86/cpu CPUID refactorings will be sent to Linus at this
merge window or the next — so I thought I'd make everyone's life "easier"
by just basing on -rc1 instead.

(The -stable trees will have trouble merging this v2 -- but at least v1
 shows the same PQ before the CPUID refactorings at tip:x86/cpu.)

Thanks a lot,

--
Ahmed S. Darwish
Linutronix GmbH