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Message-ID: <5019259.31r3eYUQgx@workhorse>
Date: Mon, 14 Apr 2025 20:30:38 +0200
From: Nicolas Frattaroli <nicolas.frattaroli@...labora.com>
To: heiko@...ech.de, Kever Yang <kever.yang@...k-chips.com>
Cc: andersson@...nel.org, Kever Yang <kever.yang@...k-chips.com>,
Shawn Lin <Shawn.lin@...k-chips.com>, Conor Dooley <conor+dt@...nel.org>,
Finley Xiao <finley.xiao@...k-chips.com>,
Frank Wang <frank.wang@...k-chips.com>, Rob Herring <robh@...nel.org>,
Detlev Casanova <detlev.casanova@...labora.com>,
linux-kernel@...r.kernel.org, Krzysztof Kozlowski <krzk+dt@...nel.org>,
linux-rockchip@...ts.infradead.org, devicetree@...r.kernel.org,
Andy Yan <andy.yan@...k-chips.com>, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v9 2/2] arm64: dts: rockchip: Add rk3576 pcie nodes
On Monday, 14 April 2025 16:51:10 Central European Summer Time Kever Yang wrote:
> rk3576 has two pcie controllers, both are pcie2x1 work with
> naneng-combphy.
>
> Signed-off-by: Kever Yang <kever.yang@...k-chips.com>
> Tested-by: Shawn Lin <Shawn.lin@...k-chips.com>
> ---
>
> Changes in v9:
> - rebase on 6.15-rc1
> - Add test tag
>
> Changes in v8: None
> Changes in v7:
> - re-order the properties.
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3:
> - Update the subject
>
> Changes in v2:
> - Update clock and reset names and sequence to pass DTB check
>
> arch/arm64/boot/dts/rockchip/rk3576.dtsi | 108 +++++++++++++++++++++++
> 1 file changed, 108 insertions(+)
>
Reviewed-by: Nicolas Frattaroli <nicolas.frattaroli@...labora.com>
Tested-by: Nicolas Frattaroli <nicolas.frattaroli@...labora.com>
Successfully used this on an ArmSoM Sige5 RK3576 board. PCIe works.
Properties look correct, though the `ranges = ` doesn't separate out the
different ranges into individual `<cells>` but this doesn't seem to make
any difference and doesn't cause any warnings either. The only added
warning is "simple-bus unit address format error" which seems like a
bug in the thing generating the warning and not the device-tree itself,
as it doesn't seem to notice that the address of the node is within the
regs array, just not as the first cell.
I think this looks good for merging, I'll also send out a Sige5 enablement
patch shortly.
Thank you!
Regards,
Nicolas Frattaroli
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