linux-kernel - Re: [PATCH v2 11/12] arm64: dts: renesas: Add initial SoC DTSI for RZ/V2N

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CA+V-a8uv4yL+CMJB-HXAmHNr25_PqPfoWAV8e5OuiAVQnizKAw@mail.gmail.com>
Date: Mon, 14 Apr 2025 09:38:34 +0100
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
Cc: Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, 
	Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Linus Walleij <linus.walleij@...aro.org>, Greg Kroah-Hartman <gregkh@...uxfoundation.org>, 
	Jiri Slaby <jirislaby@...nel.org>, Magnus Damm <magnus.damm@...il.com>, 
	linux-renesas-soc@...r.kernel.org, linux-clk@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	linux-gpio@...r.kernel.org, linux-serial@...r.kernel.org, 
	Biju Das <biju.das.jz@...renesas.com>, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v2 11/12] arm64: dts: renesas: Add initial SoC DTSI for RZ/V2N

Hi Geert,

Thank you for the review.

On Thu, Apr 10, 2025 at 11:54 AM Geert Uytterhoeven
<geert@...ux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, 7 Apr 2025 at 21:16, Prabhakar <prabhakar.csengg@...il.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > Add the initial Device Tree Source Include (DTSI) file for the Renesas
> > RZ/V2N (R9A09G056) SoC. Include support for the following components:
> >
> > - CPU (Cortex-A55 cores with operating points)
> > - External clocks (audio, qextal, rtxin)
> > - Pin controller (GPIO support)
> > - Clock Pulse Generator (CPG)
> > - System controller (SYS)
> > - Serial Communication Interface (SCIF)
> > - Secure Digital Host Interface (SDHI 0/1/2)
> > - Generic Interrupt Controller (GIC)
> > - ARMv8 timer
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > ---
> > v1->v2:
> > - Added RZV2N_Px, RZV2N_PORT_PINMUX, and RZV2N_GPIO macros in
> >   SoC DTSI as we are re-using renesas,r9a09g057-pinctrl.h
> >   in pictrl driver hence to keep the consistency with the
> >   RZ/V2H(P) SoC these macros are added.
>
> Thanks for the update!
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
> i.e. will queue in renesas-devel for v6.16.
>
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
>
> > +               pinctrl: pinctrl@...10000 {
> > +                       compatible = "renesas,r9a09g056-pinctrl";
> > +                       reg = <0 0x10410000 0 0x10000>;
> > +                       clocks = <&cpg CPG_CORE R9A09G056_IOTOP_0_SHCLK>;
> > +                       gpio-controller;
> > +                       #gpio-cells = <2>;
> > +                       gpio-ranges = <&pinctrl 0 0 96>;
> > +                       power-domains = <&cpg>;
> > +                       resets = <&cpg 0xa5>, <&cpg 0xa6>;
>
> Note that support for these resets is not yet implemented in the clock
> driver (also on RZ/V2H).  This is not an issue if the pin control
> driver does not use it.
>
Good point. I'll add the entry for both the SoCs once the initial
patches get merged.

Cheers,
Prabhakar