linux-kernel - Re: [PATCH V2 06/10] arm64: dts: imx8mm-beacon: Configure Ethernet PHY reset and GPIO IRQ

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Message-ID: <Z//B77ppZx2Xr9Dz@lizhi-Precision-Tower-5810>
Date: Wed, 16 Apr 2025 10:42:55 -0400
From: Frank Li <Frank.li@....com>
To: Adam Ford <aford173@...il.com>
Cc: linux-arm-kernel@...ts.infradead.org, aford@...conembedded.com,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>, Shawn Guo <shawnguo@...nel.org>,
	Sascha Hauer <s.hauer@...gutronix.de>,
	Pengutronix Kernel Team <kernel@...gutronix.de>,
	Fabio Estevam <festevam@...il.com>, devicetree@...r.kernel.org,
	imx@...ts.linux.dev, linux-kernel@...r.kernel.org
Subject: Re: [PATCH V2 06/10] arm64: dts: imx8mm-beacon: Configure Ethernet
 PHY reset and GPIO IRQ

On Tue, Apr 15, 2025 at 08:01:32PM -0500, Adam Ford wrote:
> The Ethernet PHY setup currently assumes that the bootloader will take the
> PHY out of reset, but this behavior is not guaranteed across all
> bootloaders. Add the reset GPIO to ensure the kernel can properly control
> the PHY reset line.
>
> Also configure the PHY IRQ GPIO to enable interrupt-driven link status
> reporting, instead of relying on polling.
>
> This ensures more reliable Ethernet initialization and improves PHY event
> handling.
>
> Signed-off-by: Adam Ford <aford173@...il.com>

Reviewed-by: Frank Li <Frank.Li@....com>
> ---
> V2:  Update commit message. No active changes.
>
>  arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
> index 9ba0cb89fa24..ed7a1be4a1a6 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
> @@ -78,6 +78,9 @@ mdio {
>  		ethphy0: ethernet-phy@0 {
>  			compatible = "ethernet-phy-ieee802.3-c22";
>  			reg = <0>;
> +			reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
> +			interrupt-parent = <&gpio1>;
> +			interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
>  		};
>  	};
>  };
> @@ -315,6 +318,7 @@ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
>  			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
>  			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
>  			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
> +			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10             0x146
>  			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22	0x19
>  		>;
>  	};
> --
> 2.48.1
>