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Message-ID: <CAP6Zq1hURTrDgScx=eN_GO5FV8vZNsaGVQLOxbZPCXSqc0Kxwg@mail.gmail.com>
Date: Wed, 16 Apr 2025 21:43:58 +0300
From: Tomer Maimon <tmaimon77@...il.com>
To: Krzysztof Kozlowski <krzk@...nel.org>
Cc: "William A. Kennington III" <william@...nnington.com>, Avi Fishman <avifishman70@...il.com>,
Tali Perry <tali.perry1@...il.com>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, openbmc@...ts.ozlabs.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64: dts: Fix nuvoton 8xx clock properties
William, thanks for the patch.
On Wed, 16 Apr 2025 at 09:55, Krzysztof Kozlowski <krzk@...nel.org> wrote:
>
> On 16/04/2025 01:25, William A. Kennington III wrote:
> > The latest iteration of the clock driver got rid of the separate clock
>
> I don't see the binding deprecated.
>
> > compatible node, merging clock and reset devices.
> >
> > Signed-off-by: William A. Kennington III <william@...nnington.com>
> > ---
> > .../boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 16 ++++++----------
> > .../boot/dts/nuvoton/nuvoton-npcm845-evb.dts | 8 ++++++++
> > 2 files changed, 14 insertions(+), 10 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> > index ecd171b2feba..4da62308b274 100644
> > --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> > +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> > @@ -47,17 +47,13 @@ ahb {
> > interrupt-parent = <&gic>;
> > ranges;
> >
> > - rstc: reset-controller@...01000 {
> > + clk: rstc: reset-controller@...01000 {
> > compatible = "nuvoton,npcm845-reset";
> > reg = <0x0 0xf0801000 0x0 0x78>;
The size of the registers offset is 0xC4 (last register is at offset 0xC0)
Therefore, the reg property should be modified as well to reg = <0x0
0xf0801000 0x0 0xC4>;
>
> So now it lacks quite a bit of address space. This must be explained in
> commit msg.
>
> > #reset-cells = <2>;
> > nuvoton,sysgcr = <&gcr>;
> > - };
> > -
> > - clk: clock-controller@...01000 {
> > - compatible = "nuvoton,npcm845-clk";
> > + clocks = <&refclk>;
> > #clock-cells = <1>;
> > - reg = <0x0 0xf0801000 0x0 0x1000>;
> > };
> >
> > apb {
> > @@ -81,7 +77,7 @@ timer0: timer@...0 {
> > compatible = "nuvoton,npcm845-timer";
> > interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> > reg = <0x8000 0x1C>;
> > - clocks = <&clk NPCM8XX_CLK_REFCLK>;
> > + clocks = <&refclk>;
>
> Not explained in commit msg.
>
>
> Best regards,
> Krzysztof
Best regards,
Tomer
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