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Message-ID: <20250416080517.feansrkpycsynk6t@vireshk-i7>
Date: Wed, 16 Apr 2025 13:35:17 +0530
From: Viresh Kumar <viresh.kumar@...aro.org>
To: Chun-Jen Tseng (曾俊仁) <Chun-Jen.Tseng@...iatek.com>
Cc: "cw00.choi@...sung.com" <cw00.choi@...sung.com>,
"rafael@...nel.org" <rafael@...nel.org>,
Project_Global_Chrome_Upstream_Group <Project_Global_Chrome_Upstream_Group@...iatek.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
"myungjoo.ham@...sung.com" <myungjoo.ham@...sung.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"kyungmin.park@...sung.com" <kyungmin.park@...sung.com>,
"linux-arm-kernel@...ts.infradead.org" <linux-arm-kernel@...ts.infradead.org>,
"matthias.bgg@...il.com" <matthias.bgg@...il.com>,
"linux-pm@...r.kernel.org" <linux-pm@...r.kernel.org>,
"linux-mediatek@...ts.infradead.org" <linux-mediatek@...ts.infradead.org>
Subject: Re: [PATCH v3 1/3] cpufreq: mediatek: using global lock avoid race
condition
On 14-04-25, 08:42, Chun-Jen Tseng (曾俊仁) wrote:
> Hi Viresh,
>
> The CCI level choose by Max_Level(LCPU & BCPU frequency) in devfreq
> driver.
> without global lock, It may choose wrong CCI level and cause system
> stall.
>
> I hope this flow is serial setting like, BCPU / LCPU set frequency ->
> set CCI level -> BCPU / LCPU set frequency -> set CCI level -> ......
>
> without global lock, it could be LCPU / BCPU set frequency -> set CCI
> level(during this time, it may change BCPU / LCPU frequency and cause
> system stall.
>
> I also can only do global lock on ccifreq_support SoC.
As explained earlier, I don't think there is a race here. May be I am
wrong. And so I need a clear code path example from you, which proves
that there is a race here.
--
viresh
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