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Message-ID: <CAMuHMdV9p9uwMUR59F+_fJiSU0b5vJWr4hHJmc4geos=48TndQ@mail.gmail.com>
Date: Thu, 17 Apr 2025 15:41:17 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Thierry Bultel <thierry.bultel.yh@...renesas.com>
Cc: thierry.bultel@...atsea.fr, linux-renesas-soc@...r.kernel.org,
paul.barker.ct@...renesas.com, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v7 02/13] dt-bindings: clock: Add cpg for the Renesas
RZ/T2H SoC
Hi Thierry,
On Thu, 3 Apr 2025 at 23:29, Thierry Bultel
<thierry.bultel.yh@...renesas.com> wrote:
> Document RZ/T2H (a.k.a r9a09g077) cpg-mssr (Clock Pulse Generator) binding.
>
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@...renesas.com>
Thanks for your patch!
> --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
> +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
> @@ -52,9 +52,15 @@ properties:
> - renesas,r8a779f0-cpg-mssr # R-Car S4-8
> - renesas,r8a779g0-cpg-mssr # R-Car V4H
> - renesas,r8a779h0-cpg-mssr # R-Car V4M
> + - renesas,r9a09g077-cpg-mssr # RZ/T2H
>
> reg:
> - maxItems: 1
> + minItems: 1
> + items:
> + - description: base address of register block 0
> + - description: base address of register block 1
> + description: base addresses of clock controller. Some controllers
> + (like r9a09g077) use two blocks instead of a single one).
Non-matching closing parenthesis at the end of the line.
> @@ -111,6 +102,44 @@ required:
> - '#clock-cells'
> - '#power-domain-cells'
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,r9a09g077-cpg-mssr
> + then:
> + properties:
> + reg:
> + minItems: 2
> + clocks:
> + minItems: 2
> + clock-names:
> + items:
> + - const: extal
There are actually two external clock inputs:
1. Crystal resonator between XTAL and EXTAL pins,
2. Clock signal input to the EXTCLKIN pin.
Given they are mutually-exclusive, and the choice is made by an
external input signal (XTALSEL) which cannot be read from software,
I think it is fine to model this as a single "extal" input clock.
> + - const: loco
LOCO is the Low-Speed On-Chip Oscillator, i.e. on-chip, and thus
not an external clock input.
> + else:
> + properties:
> + reg:
> + maxItems: 1
> + clock-names:
> + items:
> + enum:
> + - extal # All
> + - extalr # Most R-Car Gen3 and RZ/G2
> + - usb_extal # Most R-Car Gen2 and RZ/G1
> +
> + - if:
> + not:
> + properties:
> + compatible:
> + items:
> + enum:
> + - renesas,r7s9210-cpg-mssr
> + then:
> + required:
> + - '#reset-cells'
> +
> additionalProperties: false
>
> examples:
> --- /dev/null
> +++ b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
> @@ -0,0 +1,49 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> + *
> + * Copyright (C) 2025 Renesas Electronics Corp.
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__
> +#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* R9A09G077 CPG Core Clocks */
> +#define R9A09G077_CA55C0 0
> +#define R9A09G077_CA55C1 1
> +#define R9A09G077_CA55C2 2
> +#define R9A09G077_CA55C3 3
> +#define R9A09G077_SDHIHS 4
> +#define R9A09G077_CLK_PLL1_ETH_PHY 5
> +#define R9A09G077_CLK_OSC_ETH_PHY 6
> +#define R9A09G077_CLK_ETHPHY 7
I can't find these 3 clocks?
Table 7.2 "Specifications of Clock Generation Circuit (internal clock)"
Figure 7.1" Block diagram of clock generation circuit"
> +#define R9A09G077_PCLKAH 8
> +#define R9A09G077_PCLKAM 9
> +#define R9A09G077_PCLKAL 10
> +#define R9A09G077_CLK_SEL_ETH_PHY 11
I can't find this clock?
> +#define R9A09G077_DFI 12
> +#define R9A09G077_PCLKH 13
> +#define R9A09G077_PCLKM 14
> +#define R9A09G077_PCLKL 15
> +#define R9A09G077_PCLKGPTL 16
> +#define R9A09G077_PCLKSHOST 17
> +#define R9A09G077_PCLKRTC 18
> +#define R9A09G077_USB 19
> +#define R9A09G077_SPI0 20
> +#define R9A09G077_SPI1 21
> +#define R9A09G077_SPI2 22
> +#define R9A09G077_SPI3 23
R9A09G077_XSPI[0-3]?
> +#define R9A09G077_ETCLKA 24
> +#define R9A09G077_ETCLKB 25
> +#define R9A09G077_ETCLKC 26
> +#define R9A09G077_ETCLKD 27
> +#define R9A09G077_ETCLKE 28
> +#define R9A09G077_ETHCLKE 29
I can't find this clock?
> +#define R9A09G077_ETHCLK_EXTAL 30
> +#define R9A09G077_ETH_REFCLK 31
There are four of these? R9A09G077_ETH[0-3]_REFCLK?
> +#define R9A09G077_LCDC_CLKA 32
> +#define R9A09G077_LCDC_CLKP 33
I can't find these 2 clocks?
> +#define R9A09G077_CA55 34
R9A09G077_CA55S?
> +#define R9A09G077_LCDC_CLKD 35
Some clocks seem to be missing, but you can always add them later
(this file is an ABI, i.e. append-only).
> +
> +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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