linux-kernel - RE: [PATCH v7 06/13] clk: renesas: Add support for R9A09G077 SoC

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Message-ID:
 <TYCPR01MB11492BCF416760E978541AFE18ABF2@TYCPR01MB11492.jpnprd01.prod.outlook.com>
Date: Fri, 18 Apr 2025 21:22:00 +0000
From: Thierry Bultel <thierry.bultel.yh@...renesas.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
CC: "thierry.bultel@...atsea.fr" <thierry.bultel@...atsea.fr>,
	"linux-renesas-soc@...r.kernel.org" <linux-renesas-soc@...r.kernel.org>, Paul
 Barker <paul.barker.ct@...renesas.com>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, "linux-clk@...r.kernel.org"
	<linux-clk@...r.kernel.org>
Subject: RE: [PATCH v7 06/13] clk: renesas: Add support for R9A09G077 SoC

Hi Geert,

[snip]

> > +};
> > +
> > +static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
> > +       DEF_MOD("sci0", 108, R9A09G077_PCLKM),
> 
> Shouldn't that be 8 instead of 108?
> Using R9A09G077_PCLKM as the parent is a temporary simplification, right?
> 

I am probably missing something, isn’t PCKML actually the parent clock ?

Thierry