linux-kernel - Re: [PATCH v7 06/13] clk: renesas: Add support for R9A09G077 SoC

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Message-ID: <CAMuHMdVQPbP0Fi5SDN8uOJ23S=_8pqHRVR2QFS8vHNfohzae2g@mail.gmail.com>
Date: Wed, 23 Apr 2025 09:18:59 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Thierry Bultel <thierry.bultel.yh@...renesas.com>
Cc: "thierry.bultel@...atsea.fr" <thierry.bultel@...atsea.fr>, 
	"linux-renesas-soc@...r.kernel.org" <linux-renesas-soc@...r.kernel.org>, 
	Paul Barker <paul.barker.ct@...renesas.com>, 
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, 
	"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>
Subject: Re: [PATCH v7 06/13] clk: renesas: Add support for R9A09G077 SoC

Hi Thierry,

On Fri, 18 Apr 2025 at 23:22, Thierry Bultel
<thierry.bultel.yh@...renesas.com> wrote:
 > +};
> > > +
> > > +static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
> > > +       DEF_MOD("sci0", 108, R9A09G077_PCLKM),
> >
> > Shouldn't that be 8 instead of 108?
> > Using R9A09G077_PCLKM as the parent is a temporary simplification, right?
>
> I am probably missing something, isn’t PCKML actually the parent clock ?

According to Figure 7.1 ("Block diagram of clock generation circuit"),
it is PCLKSCI0, which can be switched to PCLKM.  I guess that is the
default, hence my "temporary simplification" question.

As the actual switching is controlled through the SCI's CCR3 register,
the SCI block should have two clock inputs in DT (PCLKM and PCLKSCIn),
and thus the DT bindings should be amended.  See also Figure 33.1
("SCI block diagram").

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds