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Message-ID: <CANAwSgTmmqkphvu=S8Li=O=oGNr2T7Eo8ocZpTx3kNix_CyX2w@mail.gmail.com>
Date: Mon, 21 Apr 2025 00:02:10 +0530
From: Anand Moon <linux.amoon@...il.com>
To: Jensen Huang <jensenhuang@...endlyarm.com>
Cc: Shawn Lin <shawn.lin@...k-chips.com>, Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof Wilczyński <kw@...ux.com>,
Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>, Rob Herring <robh@...nel.org>,
Bjorn Helgaas <bhelgaas@...gle.com>, Heiko Stuebner <heiko@...ech.de>,
Philipp Zabel <p.zabel@...gutronix.de>, Krzysztof Wilczyński <kwilczynski@...nel.org>,
linux-pci@...r.kernel.org, linux-rockchip@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] PCI: rockchip: Fix order of rockchip_pci_core_rsts
Hi Jensen,
On Fri, 28 Mar 2025 at 16:29, Jensen Huang <jensenhuang@...endlyarm.com> wrote:
>
> The order of rockchip_pci_core_rsts follows the previous comments suggesting
> to avoid reordering. However, reset_control_bulk_deassert() applies resets in
> reverse, which may lead to the link downgrading to 2.5 GT/s.
>
> This patch restores the deassert order and comments for core_rsts, introduced in
> commit 58c6990c5ee7 ("PCI: rockchip: Improve the deassert sequence of four reset pins").
>
> Tested on NanoPC-T4 with Samsung 970 Pro.
>
> Fixes: 18715931a5c0 ("PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function")
> Signed-off-by: Jensen Huang <jensenhuang@...endlyarm.com>
> ---
> drivers/pci/controller/pcie-rockchip.h | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h
> index 11def598534b..4f63a03d535c 100644
> --- a/drivers/pci/controller/pcie-rockchip.h
> +++ b/drivers/pci/controller/pcie-rockchip.h
> @@ -320,11 +320,15 @@ static const char * const rockchip_pci_pm_rsts[] = {
> "aclk",
> };
>
> +/*
> + * Please don't reorder the deassert sequence of the following
> + * four reset pins.
> + */
> static const char * const rockchip_pci_core_rsts[] = {
> - "mgmt-sticky",
> - "core",
> - "mgmt",
> "pipe",
> + "mgmt",
> + "core",
> + "mgmt-sticky",
> };
Thanks for this Fix. Could you add my if you can?
Reviewed-by: Anand Moon <linux.amoon@...il.com>
Thanks
-Anand
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