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Message-ID: <eff95b10-f20e-4abc-b519-36fd80843954@ti.com>
Date: Sun, 20 Apr 2025 08:25:22 +0530
From: Siddharth Vadapalli <s-vadapalli@...com>
To: "Kumar, Udit" <u-kumar1@...com>
CC: Parth Pancholi <parth105105@...il.com>, Nishanth Menon <nm@...com>,
Vignesh Raghavendra <vigneshr@...com>, Tero Kristo <kristo@...nel.org>,
Rob
Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor
Dooley <conor+dt@...nel.org>,
Siddharth Vadapalli <s-vadapalli@...com>,
Parth
Pancholi <parth.pancholi@...adex.com>,
<linux-arm-kernel@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2] arm64: dts: ti: k3-j784s4-main: Enable ACSPCIE
outputs for PCIe interfaces
On Sat, Apr 19, 2025 at 06:38:00PM +0530, Kumar, Udit wrote:
> Thanks for patch, Parth
>
> On 4/4/2025 3:42 PM, Parth Pancholi wrote:
Hello Parth,
> > From: Parth Pancholi <parth.pancholi@...adex.com>
> >
> > TI J784S4-based devices, such as the AM69 SoC, provide PCIE_REFCLK outputs
> > from the SoC, which can be used to clock external PCIe endpoint devices.
> > Each PCIE_REFCLK output is enabled via the corresponding ACSPCIE clock
> > buffer, with each buffer supporting two PADs to provide reference clocks
> > for two associated PCIe instances. The mappings are as follows:
> > - PCIe0 -> ACSPCIE1 PAD0
> > - PCIe1 -> ACSPCIE0 PAD0
> > - PCIe2 -> ACSPCIE1 PAD1
> > - PCIe3 -> ACSPCIE0 PAD1
> >
> > This patch enables each ACSPCIE module and its corresponding PADs to ensure
> > that all PCIE_REFCLK outputs are functional.
> >
> > This change have been tested on an AM69-based custom hardware platform,
> > where all four PCIe instances (PCIe0, PCIe1, PCIe2, and PCIe3) with the
> > internal PCIE_REFCLK are utilized with various endpoint devices such as
> > a WiFi card, NVMe SSD, and PCIe-to-USB bridge.
>
> You can enabling REFCLK to be out as default.
>
> There are few boards, on which this clock is either terminated at test point
> or not connected at all
>
> Example AM69 board
>
> PCIE_REFCLK2_P_OUT is not connected and PCIE_REFCLK0_P_OUT is terminated at
> test points.
>
>
> IMO, this clock to be enabled where this can be connected to PCIe EP.
>
> Let Siddharth also share his comment, where to enable these clocks board
> file or SOC file.
As Udit has pointed out, the reference clock outputs from ACSPCIE
buffers should be enabled in the board files. I will be updating the
patch that I had posted for enabling output of ACSPCIE0 PAD0 for PCIe1
by moving the changes to the board file
k3-j784s4-j742s2-evm-common.dtsi
Please update your patch accordingly. The overrides will no longer be
required as the property will be defined in the board file itself for
AM69.
Regards,
Siddharth.
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