linux-kernel - Re: [PATCH v7 06/13] clk: renesas: Add support for R9A09G077 SoC

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Message-ID: <CAMuHMdUV-kHD7BZ7zU71f8GD4sKqSnSTfoDhTU+s8wyVfXgq=A@mail.gmail.com>
Date: Wed, 23 Apr 2025 10:52:05 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Thierry Bultel <thierry.bultel.yh@...renesas.com>
Cc: "thierry.bultel@...atsea.fr" <thierry.bultel@...atsea.fr>, 
	"linux-renesas-soc@...r.kernel.org" <linux-renesas-soc@...r.kernel.org>, 
	Paul Barker <paul.barker.ct@...renesas.com>, 
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, 
	"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>
Subject: Re: [PATCH v7 06/13] clk: renesas: Add support for R9A09G077 SoC

Hi Thierry,

On Wed, 23 Apr 2025 at 09:36, Thierry Bultel
<thierry.bultel.yh@...renesas.com> wrote:
> > From: Geert Uytterhoeven <geert@...ux-m68k.org>
> > On Fri, 18 Apr 2025 at 23:22, Thierry Bultel
> > <thierry.bultel.yh@...renesas.com> wrote:
> >  > +};
> > > > > +
> > > > > +static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst =
> > {
> > > > > +       DEF_MOD("sci0", 108, R9A09G077_PCLKM),
> > > >
> > > > Shouldn't that be 8 instead of 108?
> > > > Using R9A09G077_PCLKM as the parent is a temporary simplification,
> > right?
> > >
> > > I am probably missing something, isn’t PCKML actually the parent clock ?
> >
> > According to Figure 7.1 ("Block diagram of clock generation circuit"), it
> > is PCLKSCI0, which can be switched to PCLKM.  I guess that is the default,
> > hence my "temporary simplification" question.
> >
> > As the actual switching is controlled through the SCI's CCR3 register, the
> > SCI block should have two clock inputs in DT (PCLKM and PCLKSCIn), and
> > thus the DT bindings should be amended.  See also Figure 33.1 ("SCI block
> > diagram").
> >
>
> Thanks for clarifying.
> Indeed, this is the default setting (and the one we have at this stage).
> I think that support for PCLKSCIn can be added at the time we support
> baudrate setting.

I am not sure we can do that in a clean backwards-compatible way.
Currently the DT bindings describe a single clock:

  clock-names:
    const: fck # UART functional clock

The documentation calls the two clocks:
  - Bus clock (PCLKM),
  - Operation clock (PCLKSCIn).

Which one is the functional clock? I'd say the latter...
Currently, DT says:

        clocks = <&cpg CPG_MOD 8>;
        clock-names = "fck";

and the clock driver uses PCLKM as the module's parent clock,
I think you will have a very hard time to synchronize all of the clock
driver, sci driver, and DTS when transitioning to something like:

        clocks = <&cpg CPG_MOD 8>, <&cpgR9A09G077_PCLKM>;
        clock-names = "fck", "bus";

where the modulo clock has to become PCLKSCIn (actually SCInASYNC,
as seen from the CPG).

Does that make sense, or am I missing something?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds