Message-ID: <20250424235658.0c662e67@minigeek.lan>
Date: Thu, 24 Apr 2025 23:56:58 +0100
From: Andre Przywara <andre.przywara@....com>
To: Jernej Škrabec <jernej.skrabec@...il.com>
Cc: Andrew Lunn <andrew@...n.ch>, Yixun Lan <dlan@...too.org>, Rob Herring
 <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Chen-Yu Tsai <wens@...e.org>, Samuel Holland
 <samuel@...lland.org>, Maxime Ripard <mripard@...nel.org>, Andrew Lunn
 <andrew+netdev@...n.ch>, "David S. Miller" <davem@...emloft.net>, Eric
 Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo
 Abeni <pabeni@...hat.com>, devicetree@...r.kernel.org,
 linux-arm-kernel@...ts.infradead.org, linux-sunxi@...ts.linux.dev,
 linux-kernel@...r.kernel.org, netdev@...r.kernel.org,
 clabbe.montjoie@...il.com
Subject: Re: [PATCH 4/5] arm64: dts: allwinner: a527: add EMAC0 to Radxa A5E
 board

On Thu, 24 Apr 2025 20:38:34 +0200
Jernej Škrabec <jernej.skrabec@...il.com> wrote:

> cc: Corentin LABBE
> 
> Dne četrtek, 24. april 2025 ob 16:00:37 Srednjeevropski poletni čas je Andre Przywara napisal(a):
> > On Thu, 24 Apr 2025 14:57:27 +0200
> > Andrew Lunn <andrew@...n.ch> wrote:
> > 
> > Hi Andrew,
> >   
> > > > > Just to be clear, you tried it with "rgmii-id" and the same <300> and
> > > > > <400> values?    
> > > > 
> > > > Yes, sorry, I wasn't clear: I used rgmii-id, then experimented with those
> > > > values.    
> > > 
> > > O.K, great.
> > > 
> > > I do suspect the delays are not actually in pico seconds. But without
> > > a data sheet, it is hard to know.
> > > 
> > >        if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) {
> > >                 if (val % 100) {
> > >                         dev_err(dev, "rx-delay must be a multiple of 100\n");
> > >                         return -EINVAL;
> > >                 }
> > >                 val /= 100;
> > >                 dev_dbg(dev, "set rx-delay to %x\n", val);
> > >                 if (val <= gmac->variant->rx_delay_max) {
> > >                         reg &= ~(gmac->variant->rx_delay_max <<
> > >                                  SYSCON_ERXDC_SHIFT);
> > >                         reg |= (val << SYSCON_ERXDC_SHIFT);
> > > 
> > > So the code divides by 100 and writes it to a register. But:
> > > 
> > > static const struct emac_variant emac_variant_h3 = {
> > >         .rx_delay_max = 31,
> > > 
> > > 
> > > static const struct emac_variant emac_variant_r40 = {
> > >         .rx_delay_max = 7,
> > > };
> > > 
> > > With the change from 7 to 31, did the range get extended by a factor
> > > of 4, or did the step go down by a factor of 4, and the / 100 should
> > > be / 25? I suppose the git history might have the answer in the commit
> > > message, but i'm too lazy to go look.  
> > 
> > IIRC this picosecond mapping was somewhat made up, to match common DT
> > properties. The manual just says:
> > ====================
> > 12:10  R/W  default: 0x0 ETXDC: Configure EMAC Transmit Clock Delay Chain.
> > ====================
> > 
> > So the unit is really unknown, but is probably some kind of internal cycle count.
> > The change from 7 to 31 is purely because the bitfield grew from 3 to 5
> > bits. We don't know if the underlying unit changed on the way.
> > Those values are just copied from whatever the board vendor came up with,
> > we then multiply them by 100 and put them in the mainline DT. Welcome to
> > the world of Allwinner ;-)  
> 
> IIRC Corentin asked Allwinner about units and their response was in 100 ps.
> 
> In my experience, vendor DT has proper delays specified, just 7 instead of
> 700, for example. What they get wrong, or better said, don't care, is phy
> mode. It's always set to rgmii because phy driver most of the time ignores
> this value and phy IC just uses mode set using resistors.

Ah, right, I dimly remembered there was some hardware setting, but your
mentioning of those strap resistors now tickled my memory!

So according to the Radxa board schematic, RGMII0-RXD0/RXDLY is pulled
up to VCCIO via 4.7K, while RGMII0-RXD1/TXDLY is pulled to GND (also via
4K7). According to the Motorcom YT8531 datasheet this means that RX
delay is enabled, but TX delay is not.
The Avaota board uses the same setup, albeit with an RTL8211F-CG PHY,
but its datasheet confirms it uses the same logic.

So does this mean we should say rgmii-rxid, so that the MAC adds the TX
delay? Does the stmmac driver actually support this? I couldn't find
this part by quickly checking the code.

Cheers,
Andre

> Proper way here
> would be to check schematic and set phy mode according to that. This method
> always works, except for one board, which had resistors set wrong and
> phy mode configured over phy driver was actually fix for it.
> 
> Best regards,
> Jernej
> 
> > 
> > And git history doesn't help, it's all already in the first commit for this
> > driver. I remember some discussions on the mailing list, almost 10 years
> > ago, but this requires even more digging ...
> > 
> > Cheers,
> > Andre
> > 
> > 
> >   
> > > 
> > > I briefly tried "rgmii", and I couldn't get a lease, so I quite  
> > > > confident it's rgmii-id, as you said. The vendor DTs just use "rgmii", but
> > > > they might hack the delay up another way (and I cannot be asked to look at
> > > > that awful code).
> > > > 
> > > > Cheers,
> > > > Andre    
> > 
> >   
> 
> 
> 
> 
> 

Powered by blists - more mailing lists