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Message-ID: <bf5c1f39-149e-4bb4-9c07-a38ce5a99341@kernel.org>
Date: Thu, 24 Apr 2025 10:44:23 +0200
From: Jiri Slaby <jirislaby@...nel.org>
To: Rengarajan S <rengarajan.s@...rochip.com>,
kumaravel.thiagarajan@...rochip.com, tharunkumar.pasumarthi@...rochip.com,
gregkh@...uxfoundation.org, linux-serial@...r.kernel.org,
linux-kernel@...r.kernel.org, unglinuxdriver@...rochip.com
Subject: Re: [PATCH v2 tty-next] 8250: microchip: pci1xxxx: Add PCIe Hot reset
disable support for Rev C0 and later devices
On 24. 04. 25, 5:59, Rengarajan S wrote:
> Systems that issue PCIe hot reset requests during a suspend/resume
> cycle cause PCI1XXXX device revisions prior to C0 to get its UART
> configuration registers reset to hardware default values. This results
> in device inaccessibility and data transfer failures. Starting with
> Revision C0, support was added in the device hardware (via the Hot
> Reset Disable Bit) to allow resetting only the PCIe interface and its
> associated logic, but preserving the UART configuration during a hot
> reset. This patch enables the hot reset disable feature during suspend/
> resume for C0 and later revisions of the device.
>
> v2
> Retained the original writel and simplified the hot reset condition
> v1
> Initial Commit.
This should have been under the --- line below.
> Signed-off-by: Rengarajan S <rengarajan.s@...rochip.com>
Reviewed-by: Jiri Slaby <jirislaby@...nel.org>
> ---
vvvvv here
> drivers/tty/serial/8250/8250_pci1xxxx.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
thanks,
--
js
suse labs
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