linux-kernel - RE: [PATCH v4 2/5] dt-bindings: pci: cadence: Extend compatible for new EP configurations

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID:
 <CH2PPF4D26F8E1CB9CA518EE12AFDA8B047A2842@CH2PPF4D26F8E1C.namprd07.prod.outlook.com>
Date: Fri, 25 Apr 2025 02:19:11 +0000
From: Manikandan Karunakaran Pillai <mpillai@...ence.com>
To: Conor Dooley <conor@...nel.org>,
        "hans.zhang@...tech.com"
	<hans.zhang@...tech.com>
CC: "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
        "lpieralisi@...nel.org"
	<lpieralisi@...nel.org>,
        "kw@...ux.com" <kw@...ux.com>,
        "manivannan.sadhasivam@...aro.org" <manivannan.sadhasivam@...aro.org>,
        "robh@...nel.org" <robh@...nel.org>,
        "krzk+dt@...nel.org"
	<krzk+dt@...nel.org>,
        "conor+dt@...nel.org" <conor+dt@...nel.org>,
        "peter.chen@...tech.com" <peter.chen@...tech.com>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v4 2/5] dt-bindings: pci: cadence: Extend compatible for
 new EP configurations

>
>
>On Thu, Apr 24, 2025 at 04:29:35PM +0100, Conor Dooley wrote:
>> On Thu, Apr 24, 2025 at 09:04:41AM +0800, hans.zhang@...tech.com wrote:
>> > From: Manikandan K Pillai <mpillai@...ence.com>
>> >
>> > Document the compatible property for HPA (High Performance
>Architecture)
>> > PCIe controller EP configuration.
>>
>> Please explain what makes the new architecture sufficiently different
>> from the existing one such that a fallback compatible does not work.
>>
>> Same applies to the other binding patch.
>
>Additionally, since this IP is likely in use on your sky1 SoC, why is a
>soc-specific compatible for your integration not needed?
>

The sky1 SoC support patches will be developed and submitted by the Sky1 team separately.

>>
>> Thanks,
>> Conor.
>>
>> >
>> > Signed-off-by: Manikandan K Pillai <mpillai@...ence.com>
>> > Signed-off-by: Hans Zhang <hans.zhang@...tech.com>
>> > ---
>> >  .../devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml          | 6 ++++--
>> >  1 file changed, 4 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
>b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
>> > index 98651ab22103..a7e404e4f690 100644
>> > --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
>> > +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
>> > @@ -7,14 +7,16 @@ $schema: http://devicetree.org/meta-
>schemas/core.yaml#
>> >  title: Cadence PCIe EP Controller
>> >
>> >  maintainers:
>> > -  - Tom Joseph <tjoseph@...ence.com>
>> > +  - Manikandan K Pillai <mpillai@...ence.com>
>> >
>> >  allOf:
>> >    - $ref: cdns-pcie-ep.yaml#
>> >
>> >  properties:
>> >    compatible:
>> > -    const: cdns,cdns-pcie-ep
>> > +    enum:
>> > +      - cdns,cdns-pcie-ep
>> > +      - cdns,cdns-pcie-hpa-ep
>> >
>> >    reg:
>> >      maxItems: 2
>> > --
>> > 2.47.1
>> >
>