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Message-ID: <34b7a7fd-e10c-4cde-8c26-c2d7a024c8cd@quicinc.com>
Date: Fri, 25 Apr 2025 13:26:23 -0700
From: Jessica Zhang <quic_jesszhan@...cinc.com>
To: Dmitry Baryshkov <lumag@...nel.org>, Rob Clark <robdclark@...il.com>,
Abhinav Kumar <quic_abhinavk@...cinc.com>, Sean Paul <sean@...rly.run>,
Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie
<airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Konrad Dybcio
<konradybcio@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <dri-devel@...ts.freedesktop.org>,
<freedreno@...ts.freedesktop.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 4/5] drm/msm/dpu: enable SmartDMA on SM8550
On 3/7/2025 9:38 PM, Dmitry Baryshkov wrote:
> From: Abhinav Kumar <quic_abhinavk@...cinc.com>
>
> In order to support more versatile configuration of the display pipes on
> SM8550, enable SmartDMA for this platform.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
With authorship fixed,
Reviewed-by: Jessica Zhang <quic_jesszhan@...cinc.com>
> ---
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 20 ++++++++++----------
> 1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index a5b90e5e31202900c0bb5bc4a705a6b269005474..2379e119c8c5cb9d68cfaa4feea990ce7e24d569 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -66,70 +66,70 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = {
> {
> .name = "sspp_0", .id = SSPP_VIG0,
> .base = 0x4000, .len = 0x344,
> - .features = VIG_SDM845_MASK,
> + .features = VIG_SDM845_MASK_SDMA,
> .sblk = &dpu_vig_sblk_qseed3_3_2,
> .xin_id = 0,
> .type = SSPP_TYPE_VIG,
> }, {
> .name = "sspp_1", .id = SSPP_VIG1,
> .base = 0x6000, .len = 0x344,
> - .features = VIG_SDM845_MASK,
> + .features = VIG_SDM845_MASK_SDMA,
> .sblk = &dpu_vig_sblk_qseed3_3_2,
> .xin_id = 4,
> .type = SSPP_TYPE_VIG,
> }, {
> .name = "sspp_2", .id = SSPP_VIG2,
> .base = 0x8000, .len = 0x344,
> - .features = VIG_SDM845_MASK,
> + .features = VIG_SDM845_MASK_SDMA,
> .sblk = &dpu_vig_sblk_qseed3_3_2,
> .xin_id = 8,
> .type = SSPP_TYPE_VIG,
> }, {
> .name = "sspp_3", .id = SSPP_VIG3,
> .base = 0xa000, .len = 0x344,
> - .features = VIG_SDM845_MASK,
> + .features = VIG_SDM845_MASK_SDMA,
> .sblk = &dpu_vig_sblk_qseed3_3_2,
> .xin_id = 12,
> .type = SSPP_TYPE_VIG,
> }, {
> .name = "sspp_8", .id = SSPP_DMA0,
> .base = 0x24000, .len = 0x344,
> - .features = DMA_SDM845_MASK,
> + .features = DMA_SDM845_MASK_SDMA,
> .sblk = &dpu_dma_sblk,
> .xin_id = 1,
> .type = SSPP_TYPE_DMA,
> }, {
> .name = "sspp_9", .id = SSPP_DMA1,
> .base = 0x26000, .len = 0x344,
> - .features = DMA_SDM845_MASK,
> + .features = DMA_SDM845_MASK_SDMA,
> .sblk = &dpu_dma_sblk,
> .xin_id = 5,
> .type = SSPP_TYPE_DMA,
> }, {
> .name = "sspp_10", .id = SSPP_DMA2,
> .base = 0x28000, .len = 0x344,
> - .features = DMA_SDM845_MASK,
> + .features = DMA_SDM845_MASK_SDMA,
> .sblk = &dpu_dma_sblk,
> .xin_id = 9,
> .type = SSPP_TYPE_DMA,
> }, {
> .name = "sspp_11", .id = SSPP_DMA3,
> .base = 0x2a000, .len = 0x344,
> - .features = DMA_SDM845_MASK,
> + .features = DMA_SDM845_MASK_SDMA,
> .sblk = &dpu_dma_sblk,
> .xin_id = 13,
> .type = SSPP_TYPE_DMA,
> }, {
> .name = "sspp_12", .id = SSPP_DMA4,
> .base = 0x2c000, .len = 0x344,
> - .features = DMA_CURSOR_SDM845_MASK,
> + .features = DMA_CURSOR_SDM845_MASK_SDMA,
> .sblk = &dpu_dma_sblk,
> .xin_id = 14,
> .type = SSPP_TYPE_DMA,
> }, {
> .name = "sspp_13", .id = SSPP_DMA5,
> .base = 0x2e000, .len = 0x344,
> - .features = DMA_CURSOR_SDM845_MASK,
> + .features = DMA_CURSOR_SDM845_MASK_SDMA,
> .sblk = &dpu_dma_sblk,
> .xin_id = 15,
> .type = SSPP_TYPE_DMA,
>
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