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Message-Id: <20250428-cv18xx-mbox-v3-1-ed18dfd836d1@pigmoral.tech>
Date: Mon, 28 Apr 2025 20:39:44 +0800
From: Junhui Liu <junhui.liu@...moral.tech>
To: Jassi Brar <jassisinghbrar@...il.com>, Rob Herring <robh@...nel.org>, 
 Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, Chen Wang <unicorn_wang@...look.com>, 
 Inochi Amaoto <inochiama@...il.com>, Yuntao Dai <d1581209858@...e.com>, 
 Junhui Liu <junhui.liu@...moral.tech>, 
 Paul Walmsley <paul.walmsley@...ive.com>, 
 Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, 
 Alexandre Ghiti <alex@...ti.fr>
Cc: linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, 
 sophgo@...ts.linux.dev, linux-riscv@...ts.infradead.org
Subject: [PATCH v3 1/3] dt-bindings: mailbox: add Sophgo CV18XX series SoC

From: Yuntao Dai <d1581209858@...e.com>

Introduce the mailbox module for CV18XX series SoC, which is responsible
for interchanging messages between asymmetric processors.

Signed-off-by: Yuntao Dai <d1581209858@...e.com>
Signed-off-by: Junhui Liu <junhui.liu@...moral.tech>
---
 .../bindings/mailbox/sophgo,cv1800b-mailbox.yaml   | 57 ++++++++++++++++++++++
 1 file changed, 57 insertions(+)

diff --git a/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..5815dc02189c973d681f5b4ff22a9fb7536802b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mailbox/sophgo,cv1800b-mailbox.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo CV1800/SG2000 mailbox controller
+
+maintainers:
+  - Yuntao Dai <d1581209858@...e.com>
+  - Junhui Liu <junhui.liu@...moral.tech>
+
+description: |
+  Mailboxes integrated in Sophgo CV1800/SG2000 SoCs have 8 channels, each
+  shipping an 8-byte FIFO. Any processor can write to an arbitrary channel
+  and raise interrupts to receivers. Sending messages to itself is also
+  supported.
+  Sophgo CV1800/SG2000 SoCs include the following processors, numbered as:
+  <0> Cortex-A53 (Only available on CV181X/SG200X)
+  <1> C906B
+  <2> C906L
+  <3> 8051
+
+properties:
+  compatible:
+    const: sophgo,cv1800b-mailbox
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  "#mbox-cells":
+    const: 2
+    description:
+      The first cell indicates the channel index (0-7), the second cell
+      indicates the target processor ID (0-3) to which messages are sent.
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - "#mbox-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    mailbox@...0000 {
+        compatible = "sophgo,cv1800b-mailbox";
+        reg = <0x01900000 0x1000>;
+        interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
+        #mbox-cells = <2>;
+    };

-- 
2.49.0


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