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Message-ID: <1f056b35-d455-4e65-8063-db66ab764a08@amd.com>
Date: Mon, 28 Apr 2025 08:54:51 -0500
From: "Moger, Babu" <babu.moger@....com>
To: Sean Christopherson <seanjc@...gle.com>, tglx@...utronix.de,
mingo@...hat.com, bp@...en8.de, dave.hansen@...ux.intel.com,
pbonzini@...hat.com
Cc: x86@...nel.org, hpa@...or.com, daniel.sneddon@...ux.intel.com,
jpoimboe@...nel.org, pawan.kumar.gupta@...ux.intel.com,
thomas.lendacky@....com, perry.yuan@....com, linux-kernel@...r.kernel.org,
kvm@...r.kernel.org
Subject: Re: [PATCH] x86/cpufeatures: Define X86_FEATURE_PREFETCHI (AMD)
On 4/25/25 18:23, Sean Christopherson wrote:
> On Tue, 08 Apr 2025 17:57:09 -0500, Babu Moger wrote:
>> The latest AMD platform has introduced a new instruction called PREFETCHI.
>> This instruction loads a cache line from a specified memory address into
>> the indicated data or instruction cache level, based on locality reference
>> hints.
>>
>> Feature bit definition:
>> CPUID_Fn80000021_EAX [bit 20] - Indicates support for IC prefetch.
>>
>> [...]
>
> Applied to kvm-x86 misc, with a rewritten shortlog and changelog to make it super
> clear this is KVM enabling.
Sean, Thank you.
Babu Moger
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