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Message-ID: <ece226eb37c3a7c6d37798798332ea70@kernel.org>
Date: Tue, 29 Apr 2025 12:58:14 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: Bjorn Andersson <andersson@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Konrad Dybcio <konradybcio@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Luo Jie <quic_luoj@...cinc.com>, Michael Turquette <mturquette@...libre.com>, Rob Herring <robh@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, quic_kkumarcs@...cinc.com, quic_suruchia@...cinc.com, quic_pavir@...cinc.com, quic_linchen@...cinc.com, quic_leiwei@...cinc.com, Luo Jie <quic_luoj@...cinc.com>
Subject: Re: [PATCH v2 2/4] clk: qcom: cmnpll: Add IPQ5424 SoC support
Quoting Luo Jie (2025-04-11 05:58:11)
> The CMN PLL in IPQ5424 SoC supplies the fixed clock to NSS at 300 MHZ
> and to PPE at 375 MHZ. Other output clocks from CMN PLL on this SoC,
> and their rates are same as IPQ9574.
>
> Signed-off-by: Luo Jie <quic_luoj@...cinc.com>
> ---
Acked-by: Stephen Boyd <sboyd@...nel.org>
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