linux-kernel - Re: [PATCH v2 2/4] clk: qcom: cmnpll: Add IPQ5424 SoC support

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Message-ID: <5eb5631f-8f58-44d8-a09f-4bdb4a804803@quicinc.com>
Date: Tue, 29 Apr 2025 13:29:10 +0800
From: Jie Luo <quic_luoj@...cinc.com>
To: Bjorn Andersson <andersson@...nel.org>,
        Michael Turquette
	<mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>, Rob Herring
	<robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley
	<conor+dt@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <quic_kkumarcs@...cinc.com>, <quic_suruchia@...cinc.com>,
        <quic_pavir@...cinc.com>, <quic_linchen@...cinc.com>,
        <quic_leiwei@...cinc.com>
Subject: Re: [PATCH v2 2/4] clk: qcom: cmnpll: Add IPQ5424 SoC support

Hello Stephen,

Thanks for your review on the first version of this patch series.
Gentle reminder, to re-review the updated patch for any further
comments.

Regards.

On 4/11/2025 8:58 PM, Luo Jie wrote:
> The CMN PLL in IPQ5424 SoC supplies the fixed clock to NSS at 300 MHZ
> and to PPE at 375 MHZ. Other output clocks from CMN PLL on this SoC,
> and their rates are same as IPQ9574.
> 
> Signed-off-by: Luo Jie <quic_luoj@...cinc.com>
> ---
>   drivers/clk/qcom/ipq-cmn-pll.c | 35 ++++++++++++++++++++++++++++++-----
>   1 file changed, 30 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c
> index 432d4c4b7aa6..b34d6faf67b8 100644
> --- a/drivers/clk/qcom/ipq-cmn-pll.c
> +++ b/drivers/clk/qcom/ipq-cmn-pll.c
> @@ -1,6 +1,6 @@
>   // SPDX-License-Identifier: GPL-2.0-only
>   /*
> - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
>    */
>   
>   /*
> @@ -16,6 +16,10 @@
>    * are supplied to GCC (24 MHZ as XO and 32 KHZ as sleep clock), and to PCS
>    * with 31.25 MHZ.
>    *
> + * On the IPQ5424 SoC, there is an output clock from CMN PLL to PPE at 375 MHZ,
> + * and an output clock to NSS (network subsystem) at 300 MHZ. The other output
> + * clocks from CMN PLL on IPQ5424 are the same as IPQ9574.
> + *
>    *               +---------+
>    *               |   GCC   |
>    *               +--+---+--+
> @@ -46,6 +50,7 @@
>   #include <linux/regmap.h>
>   
>   #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
> +#include <dt-bindings/clock/qcom,ipq5424-cmn-pll.h>
>   
>   #define CMN_PLL_REFCLK_SRC_SELECTION		0x28
>   #define CMN_PLL_REFCLK_SRC_DIV			GENMASK(9, 8)
> @@ -115,6 +120,20 @@ static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] = {
>   	CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL),
>   	CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL),
>   	CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL),
> +	{ /* Sentinel */ }
> +};
> +
> +static const struct cmn_pll_fixed_output_clk ipq5424_output_clks[] = {
> +	CLK_PLL_OUTPUT(IPQ5424_XO_24MHZ_CLK, "xo-24mhz", 24000000UL),
> +	CLK_PLL_OUTPUT(IPQ5424_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),
> +	CLK_PLL_OUTPUT(IPQ5424_PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL),
> +	CLK_PLL_OUTPUT(IPQ5424_NSS_300MHZ_CLK, "nss-300mhz", 300000000UL),
> +	CLK_PLL_OUTPUT(IPQ5424_PPE_375MHZ_CLK, "ppe-375mhz", 375000000UL),
> +	CLK_PLL_OUTPUT(IPQ5424_ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL),
> +	CLK_PLL_OUTPUT(IPQ5424_ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL),
> +	CLK_PLL_OUTPUT(IPQ5424_ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL),
> +	CLK_PLL_OUTPUT(IPQ5424_ETH_25MHZ_CLK, "eth-25mhz", 25000000UL),
> +	{ /* Sentinel */ }
>   };
>   
>   /*
> @@ -297,7 +316,7 @@ static struct clk_hw *ipq_cmn_pll_clk_hw_register(struct platform_device *pdev)
>   
>   static int ipq_cmn_pll_register_clks(struct platform_device *pdev)
>   {
> -	const struct cmn_pll_fixed_output_clk *fixed_clk;
> +	const struct cmn_pll_fixed_output_clk *p, *fixed_clk;
>   	struct clk_hw_onecell_data *hw_data;
>   	struct device *dev = &pdev->dev;
>   	struct clk_hw *cmn_pll_hw;
> @@ -305,8 +324,13 @@ static int ipq_cmn_pll_register_clks(struct platform_device *pdev)
>   	struct clk_hw *hw;
>   	int ret, i;
>   
> -	fixed_clk = ipq9574_output_clks;
> -	num_clks = ARRAY_SIZE(ipq9574_output_clks);
> +	fixed_clk = device_get_match_data(dev);
> +	if (!fixed_clk)
> +		return -EINVAL;
> +
> +	num_clks = 0;
> +	for (p = fixed_clk; p->name; p++)
> +		num_clks++;
>   
>   	hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, num_clks + 1),
>   			       GFP_KERNEL);
> @@ -415,7 +439,8 @@ static const struct dev_pm_ops ipq_cmn_pll_pm_ops = {
>   };
>   
>   static const struct of_device_id ipq_cmn_pll_clk_ids[] = {
> -	{ .compatible = "qcom,ipq9574-cmn-pll", },
> +	{ .compatible = "qcom,ipq9574-cmn-pll", .data = &ipq9574_output_clks },
> +	{ .compatible = "qcom,ipq5424-cmn-pll", .data = &ipq5424_output_clks },
>   	{ }
>   };
>   MODULE_DEVICE_TABLE(of, ipq_cmn_pll_clk_ids);
>