linux-kernel - Re: [PATCH 1/6] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID:
 <DS7PR19MB8883AFFD49C5E9EA39B55E7B9D8D2@DS7PR19MB8883.namprd19.prod.outlook.com>
Date: Fri, 2 May 2025 20:14:25 +0400
From: George Moussalem <george.moussalem@...look.com>
To: Rob Herring <robh@...nel.org>
Cc: Bjorn Andersson <andersson@...nel.org>,
 Michael Turquette <mturquette@...libre.com>, Stephen Boyd
 <sboyd@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>, Luo Jie <quic_luoj@...cinc.com>,
 Lee Jones <lee@...nel.org>, Konrad Dybcio <konradybcio@...nel.org>,
 linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/6] dt-bindings: clock: qcom: Add CMN PLL support for
 IPQ5018 SoC



On 5/2/25 18:17, Rob Herring wrote:
> On Fri, May 02, 2025 at 02:15:43PM +0400, George Moussalem wrote:
>> The CMN PLL block in the IPQ5018 SoC takes 96 MHZ as the reference
>> input clock. Its output clocks are the XO (24Mhz), sleep (32Khz), and
>> ethernet (50Mhz) clocks.
>>
>> Unlike IPQ9574, the CMN PLL to the ethernet block needs to be enabled
>> first in IPQ5018. Hence, add optional phandle to TCSR register space
>> and offset to do so.
>>
>> Signed-off-by: George Moussalem <george.moussalem@...look.com>
>> ---
>>   .../devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml  | 11 ++++++++---
>>   include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h         | 16 ++++++++++++++++
>>   2 files changed, 24 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
>> index cb6e09f4247f4b25105b25f4ae746c0b3ef47616..25006d65d30e20ef8e1f43537bcf3dca65bae73d 100644
>> --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
>> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
>> @@ -24,12 +24,10 @@ description:
>>   properties:
>>     compatible:
>>       enum:
>> +      - qcom,ipq5018-cmn-pll
>>         - qcom,ipq5424-cmn-pll
>>         - qcom,ipq9574-cmn-pll
>>   
>> -  reg:
>> -    maxItems: 1
>> -
>>     clocks:
>>       items:
>>         - description: The reference clock. The supported clock rates include
>> @@ -50,6 +48,13 @@ properties:
>>     "#clock-cells":
>>       const: 1
>>   
>> +  qcom,cmn-pll-eth-enable:
>> +    description: Register in TCSR to enable CMN PLL to ethernet
>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
>> +    items:
>> +        - description: phandle of TCSR syscon
>> +        - description: offset of TCSR register to enable CMN PLL to ethernet
> 
> items:
>    - items:
>        - description: phandle of TCSR syscon
>        - description: offset of TCSR register to enable CMN PLL to ethernet
> 
Fixed in next version, and validated by make dt_binding_check 
DT_SCHEMA_FILES=qcom,ipq9574-cmn-pll.yaml

Thanks,
George