linux-kernel - Re: [PATCH 0/6] Add CMN PLL clock controller support for IPQ5018

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Message-Id: <174621422446.2300145.5789096612500039953.robh@kernel.org>
Date: Fri, 02 May 2025 14:31:28 -0500
From: "Rob Herring (Arm)" <robh@...nel.org>
To: George Moussalem <george.moussalem@...look.com>
Cc: Bjorn Andersson <andersson@...nel.org>, 
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Stephen Boyd <sboyd@...nel.org>, 
 devicetree@...r.kernel.org, linux-arm-msm@...r.kernel.org, 
 Conor Dooley <conor+dt@...nel.org>, linux-clk@...r.kernel.org, 
 Konrad Dybcio <konradybcio@...nel.org>, Lee Jones <lee@...nel.org>, 
 linux-kernel@...r.kernel.org, Michael Turquette <mturquette@...libre.com>, 
 Luo Jie <quic_luoj@...cinc.com>
Subject: Re: [PATCH 0/6] Add CMN PLL clock controller support for IPQ5018


On Fri, 02 May 2025 14:15:42 +0400, George Moussalem wrote:
> The CMN PLL block of IPQ5018 supplies output clocks for XO at 24 MHZ,
> sleep at 32KHZ, and the ethernet block at 50MHZ.
> 
> This patch series extends the CMN PLL driver to support IPQ5018.
> It also adds the SoC specific header file to export the CMN PLL
> output clock specifiers for IPQ5018. The new table of output
> clocks is added for the CMN PLL of IPQ5018, which is acquired
> from the device according to the compatible.
> 
> Signed-off-by: George Moussalem <george.moussalem@...look.com>
> ---
> George Moussalem (6):
>       dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC
>       clk: qcom: ipq5018: mark XO clock as critical
>       clk: qcom: ipq-cmn-pll: Add IPQ5018 SoC support
>       dt-bindings: mfd: qcom,tcsr: Add compatible for IPQ5018
>       arm64: dts: ipq5018: Add CMN PLL node
>       arm64: dts: qcom: Update IPQ5018 xo_board_clk to use fixed factor clock
> 
>  .../bindings/clock/qcom,ipq9574-cmn-pll.yaml       | 11 +++-
>  .../devicetree/bindings/mfd/qcom,tcsr.yaml         |  1 +
>  arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts     |  3 +-
>  .../dts/qcom/ipq5018-tplink-archer-ax55-v1.dts     |  3 +-
>  arch/arm64/boot/dts/qcom/ipq5018.dtsi              | 40 +++++++++++-
>  drivers/clk/qcom/gcc-ipq5018.c                     |  2 +-
>  drivers/clk/qcom/ipq-cmn-pll.c                     | 72 ++++++++++++++++++----
>  include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h   | 16 +++++
>  8 files changed, 129 insertions(+), 19 deletions(-)
> ---
> base-commit: 8a2d53ce3c5f82683ad3df9a9a55822816fe64e7
> change-id: 20250501-ipq5018-cmn-pll-8e517de873f8
> prerequisite-change-id: 20250411-qcom_ipq5424_cmnpll-960a8f597033:v2
> prerequisite-patch-id: dc3949e10baf58f8c28d24bb3ffd347a78a1a2ee
> prerequisite-patch-id: da645619780de3186a3cccf25beedd4fefab36df
> prerequisite-patch-id: 4b5d81954f1f43d450a775bcabc1a18429933aaa
> prerequisite-patch-id: 541f835fb279f83e6eb2405c531bd7da9aacf4bd
> 
> Best regards,
> --
> George Moussalem <george.moussalem@...look.com>
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


This patch series was applied (using b4) to base:
 Base: using specified base-commit 8a2d53ce3c5f82683ad3df9a9a55822816fe64e7
 Deps: looking for dependencies matching 4 patch-ids
 Deps: Applying prerequisite patch: [PATCH v2 1/4] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5424 SoC
 Deps: Applying prerequisite patch: [PATCH v2 2/4] clk: qcom: cmnpll: Add IPQ5424 SoC support
 Deps: Applying prerequisite patch: [PATCH v2 3/4] arm64: dts: ipq5424: Add CMN PLL node
 Deps: Applying prerequisite patch: [PATCH v2 4/4] arm64: dts: qcom: Update IPQ5424 xo_board to use fixed factor clock

If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)

New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/qcom/' for 20250502-ipq5018-cmn-pll-v1-0-27902c1c4071@...look.com:

arch/arm64/boot/dts/qcom/ipq9574-rdp454.dtb: clock-controller@...00 (qcom,ipq9574-cmn-pll): 'reg' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
arch/arm64/boot/dts/qcom/ipq5424-rdp466.dtb: clock-controller@...00 (qcom,ipq5424-cmn-pll): 'reg' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dtb: clock-controller@...00 (qcom,ipq9574-cmn-pll): 'reg' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
arch/arm64/boot/dts/qcom/ipq9574-rdp453.dtb: clock-controller@...00 (qcom,ipq9574-cmn-pll): 'reg' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dtb: clock-controller@...00 (qcom,ipq5018-cmn-pll): 'reg' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dtb: clock-controller@...00 (qcom,ipq5018-cmn-pll): 'reg' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
arch/arm64/boot/dts/qcom/ipq9574-rdp449.dtb: clock-controller@...00 (qcom,ipq9574-cmn-pll): 'reg' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
arch/arm64/boot/dts/qcom/ipq9574-rdp418.dtb: clock-controller@...00 (qcom,ipq9574-cmn-pll): 'reg' does not match any of the regexes: '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#