linux-kernel - Re: [PATCH 1/6] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <8f11c588-aba8-4550-9066-c6bdda0416d1@quicinc.com>
Date: Sun, 4 May 2025 09:49:46 +0800
From: Jie Luo <quic_luoj@...cinc.com>
To: <george.moussalem@...look.com>, Bjorn Andersson <andersson@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>, Lee Jones <lee@...nel.org>,
        Konrad Dybcio
	<konradybcio@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/6] dt-bindings: clock: qcom: Add CMN PLL support for
 IPQ5018 SoC



On 5/2/2025 6:15 PM, George Moussalem via B4 Relay wrote:
> From: George Moussalem <george.moussalem@...look.com>
> 
> The CMN PLL block in the IPQ5018 SoC takes 96 MHZ as the reference
> input clock. Its output clocks are the XO (24Mhz), sleep (32Khz), and
> ethernet (50Mhz) clocks.
> 
> Unlike IPQ9574, the CMN PLL to the ethernet block needs to be enabled
> first in IPQ5018. Hence, add optional phandle to TCSR register space
> and offset to do so.
> 
> Signed-off-by: George Moussalem <george.moussalem@...look.com>
> ---
>   .../devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml  | 11 ++++++++---
>   include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h         | 16 ++++++++++++++++
>   2 files changed, 24 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
> index cb6e09f4247f4b25105b25f4ae746c0b3ef47616..25006d65d30e20ef8e1f43537bcf3dca65bae73d 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
> @@ -24,12 +24,10 @@ description:
>   properties:
>     compatible:
>       enum:
> +      - qcom,ipq5018-cmn-pll
>         - qcom,ipq5424-cmn-pll
>         - qcom,ipq9574-cmn-pll
>   
> -  reg:
> -    maxItems: 1
> -

The property 'reg' should not be removed.

>     clocks:
>       items:
>         - description: The reference clock. The supported clock rates include
> @@ -50,6 +48,13 @@ properties:
>     "#clock-cells":
>       const: 1
>   
> +  qcom,cmn-pll-eth-enable:
> +    description: Register in TCSR to enable CMN PLL to ethernet
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +        - description: phandle of TCSR syscon
> +        - description: offset of TCSR register to enable CMN PLL to ethernet
> +

This TCSR should not be a part of CMN PLL, it is the LDO controller for
the internal GEPHY in IPQ5018 SoC, which can be moved to a part of GEPHY
device.

>   required:
>     - compatible
>     - reg
> diff --git a/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..586d1c9b33b374331bef413f543c526212c18494
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h
> @@ -0,0 +1,16 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_QCOM_IPQ5018_CMN_PLL_H
> +#define _DT_BINDINGS_CLK_QCOM_IPQ5018_CMN_PLL_H
> +
> +/* CMN PLL core clock. */
> +#define IPQ5018_CMN_PLL_CLK			0
> +
> +/* The output clocks from CMN PLL of IPQ5018. */
> +#define IPQ5018_XO_24MHZ_CLK			1
> +#define IPQ5018_SLEEP_32KHZ_CLK			2
> +#define IPQ5018_ETH_50MHZ_CLK			3
> +#endif
>