linux-kernel - [PATCH v3 1/4] riscv: dts: starfive: jh7110-common: add CPU BUS PERH QSPI clocks to syscrg

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Message-ID: <20250502103101.957016-2-e@freeshell.de>
Date: Fri,  2 May 2025 03:30:41 -0700
From: E Shattow <e@...eshell.de>
To: Conor Dooley <conor@...nel.org>,
	Emil Renner Berthing <kernel@...il.dk>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>,
	Alexandre Ghiti <alex@...ti.fr>
Cc: linux-kernel@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-riscv@...ts.infradead.org,
	E Shattow <e@...eshell.de>
Subject: [PATCH v3 1/4] riscv: dts: starfive: jh7110-common: add CPU BUS PERH QSPI clocks to syscrg

Add syscrg clock assignments for CPU, BUS, PERH, and QSPI as required by
boot loader before kernel.

Signed-off-by: E Shattow <e@...eshell.de>
---
 arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
index c2f70f5e2918..f1489e9bb83e 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
@@ -353,9 +353,17 @@ &spi0 {
 };
 
 &syscrg {
-	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>,
+	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
+			  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
+			  <&syscrg JH7110_SYSCLK_PERH_ROOT>,
+			  <&syscrg JH7110_SYSCLK_QSPI_REF>,
+			  <&syscrg JH7110_SYSCLK_CPU_CORE>,
 			  <&pllclk JH7110_PLLCLK_PLL0_OUT>;
-	assigned-clock-rates = <500000000>, <1500000000>;
+	assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
+				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
+				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
+				 <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
+	assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1500000000>;
 };
 
 &sysgpio {
-- 
2.49.0