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Message-ID: <7075d026-9be0-491b-af1a-e7d0565e976d@quicinc.com>
Date: Fri, 2 May 2025 16:38:09 +0530
From: Imran Shaik <quic_imrashai@...cinc.com>
To: Taniya Das <quic_tdas@...cinc.com>,
Bjorn Andersson
<andersson@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
"Stephen
Boyd" <sboyd@...nel.org>
CC: Ajit Pandey <quic_ajipan@...cinc.com>,
Jagadeesh Kona
<quic_jkona@...cinc.com>,
<linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 2/2] clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS
clocks
On 4/14/2025 2:30 PM, Taniya Das wrote:
> Update the force mem core bit for UFS ICE clock and UFS PHY AXI clock to
> force the core on signal to remain active during halt state of the clk.
> If force mem core bit of the clock is not set, the memories of the
> subsystem will not retain the logic across power states. This is
> required for the MCQ feature of UFS.
>
> Signed-off-by: Taniya Das <quic_tdas@...cinc.com>
> ---
> drivers/clk/qcom/gcc-x1e80100.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
Reviewed-by: Imran Shaik <quic_imrashai@...cinc.com>
Thanks,
Imran
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