linux-kernel - [PATCH v2 0/9] add Voyager board support

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Message-ID: <20250503151829.605006-1-ben717@andestech.com>
Date: Sat, 3 May 2025 23:18:20 +0800
From: Ben Zong-You Xie <ben717@...estech.com>
To:
CC: <devicetree@...r.kernel.org>, <linux-riscv@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <paul.walmsley@...ive.com>,
        <palmer@...belt.com>, <aou@...s.berkeley.edu>, <alex@...ti.fr>,
        <robh@...nel.org>, <krzk+dt@...nel.org>, <conor+dt@...nel.org>,
        <tglx@...utronix.de>, <daniel.lezcano@...aro.org>,
        <prabhakar.mahadev-lad.rj@...renesas.com>, <tim609@...estech.com>,
        "Ben
 Zong-You Xie" <ben717@...estech.com>
Subject: [PATCH v2 0/9] add Voyager board support

The Voyager is a 9.6” x 9.6” Micro ATX form factor development board
including Andes QiLai SoC. This patch series adds minimal device tree
files for the QiLai SoC and the Voyager board [1].

Now only support basic uart drivers to boot up into a basic console. Other
features will be added later.

[1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
---
Changelog:

v1->v2:
  - Add Rob's Reviewed-by tag to patch 2.
  - Add Rob's Acked-by tag to patch 3.
  - Add detailed descriptions to PLIC_SW and PLMT0.
  - Add Rob's Acked-by tag to patch 6.
  - Move the aliases node and memory node from qilai.dtsi to qilai-voyager.dts.
  - Drop "status = okay" in each CPU node since the status property is by
    default "okay".
  - Reorder the nodes in qilai.dtsi by unit address in ascending order.
  - Add myself as the maintainer of Andes's SoC tree.

v1: https://lore.kernel.org/all/20250407104937.315783-1-ben717@andestech.com/
---
Ben Zong-You Xie (9):
  riscv: add Andes SoC family Kconfig support
  dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings
  dt-bindings: interrupt-controller: add Andes QiLai PLIC
  dt-bindings: interrupt-controller: add Andes machine-level software
    interrupt controller
  dt-bindings: timer: add Andes machine timer
  dt-bindings: cache: ax45mp-cache: allow variable cache-sets for Andes
    L2 cache
  riscv: dts: andes: add QiLai SoC device tree
  riscv: dts: andes: add Voyager board device tree
  riscv: defconfig: enable Andes SoC

 .../cache/andestech,ax45mp-cache.yaml         |   2 +-
 .../andestech,plicsw.yaml                     |  54 +++++
 .../sifive,plic-1.0.0.yaml                    |   1 +
 .../devicetree/bindings/riscv/andes.yaml      |  25 +++
 .../bindings/timer/andestech,plmt0.yaml       |  53 +++++
 MAINTAINERS                                   |   9 +
 arch/riscv/Kconfig.errata                     |   2 +-
 arch/riscv/Kconfig.socs                       |   9 +
 arch/riscv/boot/dts/Makefile                  |   1 +
 arch/riscv/boot/dts/andes/Makefile            |   2 +
 arch/riscv/boot/dts/andes/qilai-voyager.dts   |  28 +++
 arch/riscv/boot/dts/andes/qilai.dtsi          | 186 ++++++++++++++++++
 arch/riscv/configs/defconfig                  |   1 +
 13 files changed, 371 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
 create mode 100644 Documentation/devicetree/bindings/riscv/andes.yaml
 create mode 100644 Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
 create mode 100644 arch/riscv/boot/dts/andes/Makefile
 create mode 100644 arch/riscv/boot/dts/andes/qilai-voyager.dts
 create mode 100644 arch/riscv/boot/dts/andes/qilai.dtsi

--
2.34.1