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Message-ID: <41032f89-4ff3-48b4-8f01-afa793ca9990@ghiti.fr>
Date: Tue, 6 May 2025 12:58:01 +0200
From: Alexandre Ghiti <alex@...ti.fr>
To: Clément Léger <cleger@...osinc.com>,
"open list:DOCUMENTATION" <linux-doc@...r.kernel.org>,
open list <linux-kernel@...r.kernel.org>,
"open list:RISC-V ARCHITECTURE" <linux-riscv@...ts.infradead.org>,
"open list:KERNEL SELFTEST FRAMEWORK" <linux-kselftest@...r.kernel.org>
Cc: Jonathan Corbet <corbet@....net>, Paul Walmsley
<paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>, Shuah Khan <shuah@...nel.org>,
Andrew Jones <ajones@...tanamicro.com>,
Samuel Holland <samuel.holland@...ive.com>
Subject: Re: [PATCH v2 1/5] riscv: misaligned: factorize trap handling
Hi Clément,
On 22/04/2025 18:23, Clément Léger wrote:
> Since both load/store and user/kernel should use almost the same path and
> that we are going to add some code around that, factorize it.
>
> Signed-off-by: Clément Léger <cleger@...osinc.com>
> ---
> arch/riscv/kernel/traps.c | 66 +++++++++++++++++++++------------------
> 1 file changed, 36 insertions(+), 30 deletions(-)
>
> diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
> index 8ff8e8b36524..b1d991c78a23 100644
> --- a/arch/riscv/kernel/traps.c
> +++ b/arch/riscv/kernel/traps.c
> @@ -198,47 +198,53 @@ asmlinkage __visible __trap_section void do_trap_insn_illegal(struct pt_regs *re
> DO_ERROR_INFO(do_trap_load_fault,
> SIGSEGV, SEGV_ACCERR, "load access fault");
>
> -asmlinkage __visible __trap_section void do_trap_load_misaligned(struct pt_regs *regs)
> +enum misaligned_access_type {
> + MISALIGNED_STORE,
> + MISALIGNED_LOAD,
> +};
> +static const struct {
> + const char *type_str;
> + int (*handler)(struct pt_regs *regs);
> +} misaligned_handler[] = {
> + [MISALIGNED_STORE] = {
> + .type_str = "Oops - store (or AMO) address misaligned",
> + .handler = handle_misaligned_store,
> + },
> + [MISALIGNED_LOAD] = {
> + .type_str = "Oops - load address misaligned",
> + .handler = handle_misaligned_load,
> + },
> +};
> +
> +static void do_trap_misaligned(struct pt_regs *regs, enum misaligned_access_type type)
> {
> - if (user_mode(regs)) {
> + irqentry_state_t state;
> +
> + if (user_mode(regs))
> irqentry_enter_from_user_mode(regs);
> + else
> + state = irqentry_nmi_enter(regs);
>
> - if (handle_misaligned_load(regs))
> - do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc,
> - "Oops - load address misaligned");
> + if (misaligned_handler[type].handler(regs))
> + do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc,
> + misaligned_handler[type].type_str);
>
> + if (user_mode(regs))
> irqentry_exit_to_user_mode(regs);
> - } else {
> - irqentry_state_t state = irqentry_nmi_enter(regs);
> -
> - if (handle_misaligned_load(regs))
> - do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc,
> - "Oops - load address misaligned");
> -
> + else
> irqentry_nmi_exit(regs, state);
> - }
> }
>
> -asmlinkage __visible __trap_section void do_trap_store_misaligned(struct pt_regs *regs)
> +asmlinkage __visible __trap_section void do_trap_load_misaligned(struct pt_regs *regs)
> {
> - if (user_mode(regs)) {
> - irqentry_enter_from_user_mode(regs);
> -
> - if (handle_misaligned_store(regs))
> - do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc,
> - "Oops - store (or AMO) address misaligned");
> -
> - irqentry_exit_to_user_mode(regs);
> - } else {
> - irqentry_state_t state = irqentry_nmi_enter(regs);
> -
> - if (handle_misaligned_store(regs))
> - do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc,
> - "Oops - store (or AMO) address misaligned");
> + do_trap_misaligned(regs, MISALIGNED_LOAD);
> +}
>
> - irqentry_nmi_exit(regs, state);
> - }
> +asmlinkage __visible __trap_section void do_trap_store_misaligned(struct pt_regs *regs)
> +{
> + do_trap_misaligned(regs, MISALIGNED_STORE);
> }
> +
> DO_ERROR_INFO(do_trap_store_fault,
> SIGSEGV, SEGV_ACCERR, "store (or AMO) access fault");
> DO_ERROR_INFO(do_trap_ecall_s,
Reviewed-by: Alexandre Ghiti <alexghiti@...osinc.com>
Thanks,
Alex
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