linux-kernel - Re: [PATCH v2 2/5] riscv: misaligned: enable IRQs while handling misaligned accesses

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <7db8ae4f-4cde-43b4-9ec5-5a8818d79637@ghiti.fr>
Date: Tue, 6 May 2025 13:07:58 +0200
From: Alexandre Ghiti <alex@...ti.fr>
To: Clément Léger <cleger@...osinc.com>,
 "open list:DOCUMENTATION" <linux-doc@...r.kernel.org>,
 open list <linux-kernel@...r.kernel.org>,
 "open list:RISC-V ARCHITECTURE" <linux-riscv@...ts.infradead.org>,
 "open list:KERNEL SELFTEST FRAMEWORK" <linux-kselftest@...r.kernel.org>
Cc: Jonathan Corbet <corbet@....net>, Paul Walmsley
 <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>,
 Albert Ou <aou@...s.berkeley.edu>, Shuah Khan <shuah@...nel.org>,
 Andrew Jones <ajones@...tanamicro.com>,
 Samuel Holland <samuel.holland@...ive.com>
Subject: Re: [PATCH v2 2/5] riscv: misaligned: enable IRQs while handling
 misaligned accesses

On 22/04/2025 18:23, Clément Léger wrote:
> We can safely reenable IRQs if coming from userspace. This allows to
> access user memory that could potentially trigger a page fault.
>
> Fixes: b686ecdeacf6 ("riscv: misaligned: Restrict user access to kernel memory")
> Signed-off-by: Clément Léger <cleger@...osinc.com>
> ---
>   arch/riscv/kernel/traps.c | 12 ++++++++----
>   1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
> index b1d991c78a23..9c83848797a7 100644
> --- a/arch/riscv/kernel/traps.c
> +++ b/arch/riscv/kernel/traps.c
> @@ -220,19 +220,23 @@ static void do_trap_misaligned(struct pt_regs *regs, enum misaligned_access_type
>   {
>   	irqentry_state_t state;
>   
> -	if (user_mode(regs))
> +	if (user_mode(regs)) {
>   		irqentry_enter_from_user_mode(regs);
> -	else
> +		local_irq_enable();
> +	} else {
>   		state = irqentry_nmi_enter(regs);
> +	}
>   
>   	if (misaligned_handler[type].handler(regs))
>   		do_trap_error(regs, SIGBUS, BUS_ADRALN, regs->epc,
>   			      misaligned_handler[type].type_str);
>   
> -	if (user_mode(regs))
> +	if (user_mode(regs)) {
> +		local_irq_disable();
>   		irqentry_exit_to_user_mode(regs);
> -	else
> +	} else {
>   		irqentry_nmi_exit(regs, state);
> +	}
>   }
>   
>   asmlinkage __visible __trap_section void do_trap_load_misaligned(struct pt_regs *regs)


Reviewed-by: Alexandre Ghiti <alexghiti@...osinc.com>

Thanks,

Alex