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Message-ID: <alpine.DEB.2.21.2505060059010.31828@angie.orcam.me.uk>
Date: Tue, 6 May 2025 14:51:51 +0100 (BST)
From: "Maciej W. Rozycki" <macro@...am.me.uk>
To: Borislav Petkov <bp@...en8.de>
cc: "H. Peter Anvin" <hpa@...or.com>, Ingo Molnar <mingo@...nel.org>, 
    linux-kernel@...r.kernel.org, "Ahmed S . Darwish" <darwi@...utronix.de>, 
    Andrew Cooper <andrew.cooper3@...rix.com>, 
    Ard Biesheuvel <ardb@...nel.org>, Arnd Bergmann <arnd@...nel.org>, 
    Dave Hansen <dave.hansen@...ux.intel.com>, 
    John Ogness <john.ogness@...utronix.de>, 
    Linus Torvalds <torvalds@...ux-foundation.org>, 
    Peter Zijlstra <peterz@...radead.org>, 
    Thomas Gleixner <tglx@...utronix.de>, 
    John Paul Adrian Glaubitz <glaubitz@...sik.fu-berlin.de>
Subject: Re: [RFC PATCH 0/15] x86: Remove support for TSC-less and CX8-less
 CPUs

On Mon, 5 May 2025, Borislav Petkov wrote:

> > One thing that happened with i386 was that we found out that the only
> > remaining "users" were people dragging out an old machine to test if the
> > kernel still booted.
> 
> Follow this thread:
> 
> https://lore.kernel.org/r/CANpbe9Wm3z8fy9HbgS8cuhoj0TREYEEkBipDuhgkWFvqX0UoVQ@mail.gmail.com
> 
> People booting latest kernel on 486 without CPUID support. 

 No such hardware here:

processor	: 0
vendor_id	: GenuineIntel
cpu family	: 4
model		: 3
model name	: 486 DX/2
stepping	: 5
fdiv_bug	: no
f00f_bug	: no
coma_bug	: no
fpu		: yes
fpu_exception	: yes
cpuid level	: 1
wp		: yes
flags		: fpu vme cpuid
bugs		: itlb_multihit
bogomips	: 32.56
clflush size	: 32
cache_alignment	: 32
address sizes	: 32 bits physical, 32 bits virtual
power management:

Sadly it's not one with 4MiB page support (that would be stepping 6).

> There's stable and older kernels, those folks can use those and that's it.

 Doesn't work for ongoing driver maintenance (and yes, distractions such 
as this only keep me from taking care of outstanding stuff, like figuring 
out why the defxx driver reproducibly crashes with my POWER9 box running 
glibc verification remotely for my RISC-V box; it's all intertwined and an 
issue in one place affects other ones, sigh).

  Maciej

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