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Message-ID: <87wmatn5g3.ffs@tglx>
Date: Tue, 06 May 2025 17:07:24 +0200
From: Thomas Gleixner <tglx@...utronix.de>
To: Lorenzo Pieralisi <lpieralisi@...nel.org>, Marc Zyngier
<maz@...nel.org>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski
<krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Catalin Marinas
<catalin.marinas@....com>, Will Deacon <will@...nel.org>
Cc: Arnd Bergmann <arnd@...db.de>, Sascha Bischoff
<sascha.bischoff@....com>, Timothy Hayes <timothy.hayes@....com>, "Liam R.
Howlett" <Liam.Howlett@...cle.com>, Mark Rutland <mark.rutland@....com>,
Jiri Slaby <jirislaby@...nel.org>, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, Lorenzo
Pieralisi <lpieralisi@...nel.org>
Subject: Re: [PATCH v3 22/25] irqchip/gic-v5: Add GICv5 LPI/IPI support
On Tue, May 06 2025 at 14:23, Lorenzo Pieralisi wrote:
> +static int __init gicv5_irs_init_ist(struct gicv5_irs_chip_data *irs_data)
> +{
> + u32 lpi_id_bits, idr2_id_bits, idr2_min_lpi_id_bits,
> + l2_iste_sz, l2sz, l2_iste_sz_split, idr2;
Please don't do that. That's horrible to read. If it does not fit into a
single line, make it
u32 a,....,h;
u32 i,...,m;
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