linux-kernel - Re: [PATCH v2 6/9] dt-bindings: cache: ax45mp-cache: allow variable cache-sets for Andes L2 cache

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Message-ID: <20250506-clammy-punctuate-6cb07dd0e81e@spud>
Date: Tue, 6 May 2025 17:23:21 +0100
From: Conor Dooley <conor@...nel.org>
To: Ben Zong-You Xie <ben717@...estech.com>
Cc: devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
	linux-kernel@...r.kernel.org, paul.walmsley@...ive.com,
	palmer@...belt.com, aou@...s.berkeley.edu, alex@...ti.fr,
	robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
	tglx@...utronix.de, daniel.lezcano@...aro.org,
	prabhakar.mahadev-lad.rj@...renesas.com, tim609@...estech.com
Subject: Re: [PATCH v2 6/9] dt-bindings: cache: ax45mp-cache: allow variable
 cache-sets for Andes L2 cache

On Sat, May 03, 2025 at 11:18:26PM +0800, Ben Zong-You Xie wrote:
> The current device tree binding for the Andes AX45MP L2 cache enforces
> a fixed number of cache-sets (1024). However, there are 2048 cache-sets in
> the QiLai SoC. This change allows both 1024 and 2048 as valid values for
> "cache-sets".
> 
> Signed-off-by: Ben Zong-You Xie <ben717@...estech.com>
> Acked-by: Rob Herring (Arm) <robh@...nel.org>

Applied, thanks.

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